Abstract: An M-bit digital signal, the most significant bit (MSB) thereof and an integer K are added to produce a sum which is truncated by N least significant bits to provide a symmetrically rounded bit-reduced digital output signal. The MSB may be applied in true or complemented form to the adder for selecting wide or narrow rounding modes having different numbers of output zeros disposed about a point of symmetry for a given input signal change. Advantageously, undesirable direct current (DC) shifts due to least significant bit (LSB) reduction in digital video, audio or similar applications are prevented.

Abstract: A complementary push-pull emitter follower amplifier is coupled between the output of a high voltage driver amplifier and the cathode of a kinescope for reducing the effective capacitance presented to the driver amplifier that is attributable to the kinescope cathode, socket, spark gaps and related stray capacitances. A secondary undesired capacitance loading of the amplifier attributable to the collector to base capacitances of the follower amplifier is effectively reduced by regulating the collector emitter voltages of the push-pull follower output transistors at respective substantially constant values thereby improving parameters such as the slew rate and bandwidth of the overall video display system.

Abstract: An input signal (IN) and a threshold signal (Vt) are coupled to an output terminal (2) via the base-emitter paths of first (Q1) and second (Q2) transistors having respective collector electrodes connected to a supply voltage source (3). The output terminal (2) is coupled to a source of reference potential (4) via a first resistor (Re) and is coupled via a second resistor (Rd) to a selected plate of a capacitor (C1) that is connected between the collector and base electrodes of the second transistor (Q2). Circuit impedances are scaled such that Re>Rd>R1 wherein Re and Rd are the values of the first and second resistors, respectively, and R1 is a component of the output impedance of the threshold signal source (5).

Abstract: A digital filter (20,30) separates an M-bit (12) chrominance component (C12) from an N-bit (8) digital composite video signal (CV) supplied thereto, M (12) being greater than N (8) due to arithmetic operations (24,44,46,50) required for the separation. The separated M bit chrominance component is reduced to N-bits and subtracted from the composite video signal to provide a separated luminance component. For bit reduction, the separated chrominance component (C12) is subjected to symmetrical rounding (100A or 100B and 104) and limiting (104). Advantageously, symmetrical rounding of the chrominance component provides reduces a tendency for the luminance component to exhibit contouring when displayed.

Abstract: Audio bus receiver includes a pair of bipolar transistors each having a base coupled via a respective resistor to a respective bus receiver input terminal, each having an emitter that is diode coupled to a respective current source and each having a collector coupled via a respective load resistor to a source of reference potential. The emitters are coupled together via a gain control resistor and the collectors are coupled to an output terminal via a differential amplifier. Advantageously, the receiver avoids loading the bus under power-down conditions without requiring the use of stand-by power supplies. Additionally, high common mode rejection is achieved without need for precision matching of components and only a single supply voltage is required for operation.

Abstract: A subtractor (106) forms a difference signal (D) from a video input signal (C) and a further signal (M) supplied thereto. The difference signal is limited (108) and attenuated (110) and the resultant signal (F) is combined (112) with the video input signal for providing a noise reduced video output signal (H). A delay circuit (202), responsive to the video output signal, provides field (A) and frame (B) delayed video signals. A selection circuit (220) selects a median value (M) of the field delayed video signal, the frame delayed video signal and the video input signal as the further signal for application to the subtractor. Advantageously, the further signal provides the dual functions of (1) facilitating the noise reduction of the output signal and (2) concurrently reducing the occurrence of potential motion artifacts to a very substantial degree.

Abstract: A binary number is generated representative of net motion during a field interval of an interlaced video signal from which a field to field difference signal is derived having a sign bit and a group of magnitude bits. The magnitude bits are compared with a first threshold to provide a first threshold indicating signal which, with the sign bit, are applied via respective bus lines to each correlator of a group of five correlators. The correlators are addressed using variable modulo addressing to detect patterns representative of 2--2 pull down and 3-2 pull down film originated frames. Logic is provided for detecting when one and only one of the five correlators indicates film detection to verify film mode operation. Error reduction is further enhanced by comparing the field difference signal with a second threshold, higher than the first, to provide a second thresold indicating signal to each correlator via a second bus.

Abstract: A picture in picture (PIP) video signal is applied to a display device via a non-linear processor that is enabled during display of a main picture component and disabled during display of an inset picture component responsive to a PIP identification signal. The non-linear processor is formed in an integrated circuit which includes a pin for connection to a capacitor that stores peak levels of the PIP video signal. The PIP identification signal is subjected to a voltage level translation for varying the pin voltage over a range of values, .DELTA.V, for facilitating ON/OFF operation of the non-linear processor and is applied to a selected plate of the capacitor for varying the pin voltage without substantial alternation of charge stored within the capacitor whereby only a single pin is required for both capacitor storage and on/off control of the non-linear processor and undesirable visual artifacts, such as "trailing contrast bars", are avoided.

Abstract: Motion compensated video output signal (SO) produced by a soft switching or "fading" (SSW) between the a motion compensated interpolation (MCI) and a "fallback" mode (FFI) (e.g., intra-field), controlled by a "measure of confidence" (CF) in the reliability of the estimated motion vector. The confidence measure includes the following two components, namely: (i) a "basic confidence measure" (e.g., a block based, minimum motion estimation error (BME) and (ii) a measure based on the motion velocity or "speed" of movement of the motion vector or its horizontal (MVX) and vertical components (MVY).

Abstract: PLL apparatus for generating an oscillatory signal phase locked to a component of a further signal comprises a variable oscillator for generating the oscillatory signal and a source of the further signal. A phase detector responsive to the oscillatory signal and to the component of the further signal, provides a phase error signal which is coupled to the variable oscillator via a limiter. Circuit means are provided for controlling the limiting level of the limiter. The dual limiting substantially improves the loop noise tolerance and reduces the loop sensitivity to occasional phase reversals of the component of the further signal. Additional enhancements to loop stability and noise immunity are provided by an unlock detector which detects and totalizes phase rotations in a selected area of a phase plane and by a phase wrap detector which maintains a lock indication during phase angle wrapping.

Abstract: A current source (70) is coupled to supply an output current to a circuit node (60) proportional to a video input signal (R). A first resistor (65), coupled between the circuit node (60) and a source of supply voltage (68), develops an amplified video signal which is coupled from the circuit node to the cathode (K1) of a kinescope (20) via a second resistor (85). A capacitor (100 or 110) is provided having a first electrode coupled to the cathode (K1) of the kinescope (20) and having a second electrode coupled to the circuit node (60) via an amplifier(90). Advantageously, the combined resistance of the two resistors imparts gamma correction to the kinescope, the capacitor and amplifier compensate for stray capacitance associated with the cathode without subjecting low frequency components to any possibility of distortion in the amplifier. Additionally, the capacitance (110) may be varied as a function of the beam current for stabilizing the overall driver amplifier frequency response.

Abstract: A composite video input signal is combined with a noise reduction signal to form a noise reduced first video signal which is delayed by multiple time periods of (i) one line less one-half color cycle, (ii) one line and (iii) one line plus one-half color cycle to form respective ones of first, second and third time delayed signals. The first and third delayed signals are combined to form an averaged signal from which a subtractor subtracts the composite video input signal. The resultant difference signal is limited to form the noise reduction signal. The noise reduced first video signal and the second delayed video signal are combined in an output circuit to provide noise reduced and separated chrominance and luminance output signals.

Abstract: Video signals of interlaced form are first converted to progressive scan (non-interlaced) form and then picture elements are generated that lie between the "progressive" picture elements and are interpolated by a vertical one-half (1/2) line shuffling by application of a vertical averaging. The interpolated picture elements are buffer stored and are read out again at twice the frame repetition rate whereby each second line of the stored interpolated picture elements is emitted delayed in time by 10 milli-seconds. Fields in the format 100 Hz, 2:1 interlace thereby ensue. Advantageously, interpolated picture elements are used in all of the output fields thereby avoiding picture disturbences at the frame rate (25 Hz) of the original video signal. For increasing the subjective vertical sharpness, a vertical peaking may additionally be carried out.

Abstract: A one-bit adder includes a carry stage and an adding stage and is constructed in a fast CMOS complementary pass transistor logic with complementary analog CMOS switches in the adding stage which consist of a PMOS and an NMOS transistor. The source of the PMOS transistor is connected with the drain of the NMOS transistor and the drain of the PMOS transistor is connected with the source of the NMOS transistor. The gate of the PMOS transistor receives inverted signals with respect to the gate of the NMOS transistor. Two partial output sum signals are generated by two of the switches which are connected with the input and with the output, respectively, of an inverter and the output sum signal of the adder is available at the output of the inverter.

Abstract: For improving motion portrayal and reducing undesirable artifacts, e.g., double images and "mouse teeth" structure, each pixel of intermediate fields in a field rate up-conversion system is determined from nearby pixels in the existing fields using an adaptive linear filtering method (or apparatus) which provides: calculation of sums of differences (one or more for each pixel involved in the adaptive filter); calculation of basic coefficients (one for each pixel involved in the adaptive filter); one-dimensional median filtering of the coefficients; two-dimensional linear filtering of coefficients; normalization of coefficients; calculation of main interpolated pixel values; and correction of interpolation in the case of fast motion.

Abstract: A video signal is applied to a kinescope having scan velocity modulation for improving picture sharpness in the vertical direction. Pictures from video signals of a type having non-interpolated and vertically interpolated lines (e.g., interlace-progressive up-converted) will tend to exhibit a significant reduction of sharpness in vertical direction. This problem is corrected by applying scan velocity modulation only to the interpolated lines of the video signal. Furthermore, the vertical deflection is restricted to horizontal structures or real vertical transitions, respectively. In order to have a high noise immunity of this sensitive processing, the resulting luminance amplitude of the shifted line as well as the vertical deflection is controlled to be strongly dependent on the current video signal (soft decision).

Abstract: A noisy input signal x is filtered with a restoration filter of median type to generate a filtered input signal y. The sum of the absolute differences between filtered and unfiltered signal is calculated for each position of a sliding window within the input signal representing a local estimate of the noise, and is combined with a global measure of the input signal noise to compute two coefficients a and b which are respectively applied to the unfiltered and filtered signal to generate the output signal z=a*x+b*y which is both globally and locally adapted to the structure of displayed images. Advantageously different kinds of filters operate in parallel, whereby the kind of filter elected is locally adapted to the picture activity.

Abstract: A controllable current source in an AKB circuit applies a measurement current to a kinescope driver amplifier during selected lines of the vertical interval of a video input signal to induce a beam current in a kinescope coupled to the driver amplifier. A comparison circuit compares samples of the beam current obtained during the selected lines with a reference signal and applies a correction current to the driver amplifier for regulating a parameter (e.g., black level) of images displayed by the kinescope. A signal source, coupled to the measurement current source, inhibits production of the measurement current during retrace portions of the selected lines and enables production of the measurement current during trace portions of the selected lines. Advantageously, the signal source provides suppression of visual artifacts due to AKB operation when using direct view or projection kinescopes of a type in which pincushion correction is not applied during line retrace intervals.

Abstract: For progressive scan conversion adjacent fields cannot be used to interpolate moving objects because motion blur will be introduced then. The most simple solution is to insert the average of the two adjacent lines for each missing line. A technique superior to vertical averaging represents the DIAG3 algorithm, where according to the found minimum gradient the orientation of the interpolation filter is chosen. But in case of high diagonal frequencies interpolation errors will occur. Therefore it is tested if the reconstructed pixel value exceeds or falls below the pixel values in the two adjacent lines of the input signal. If this happens, instead of one of the detected diagonal directions the vertical direction is taken, it.e. a vertical averaging is carried out.

Abstract: A bias source (R7,R8,C24) connected to a summing amplifier (Q1) produces a first DC bias at the amplifier input (emitter) and a second DC bias at the amplifier output (collector). A first circuit node (B) is AC coupled (22) to a luminance signal source (Y1, 18), DC coupled via a first resistor (R4) to the input of the summing amplifier and DC coupled via a first amplifier (28) to a luminance load (Y3,30). A second circuit node (A) is AC coupled (20) to a chrominance signal source (C1,18), DC coupled via a second resistor (R3) to the input (emitter, Q1) of the summing amplifier and DC coupled via a second amplifier (26) to a chrominance signal load (C3,30). A third amplifier (Q2) provides DC coupling of the output of the summing amplifier (Q1) to a composite video signal load (E,40).