Abstract: A capacitor structure having a re-oxide layer on a nitride layer, wherein an interface between the nitride layer and the re-oxide layer includes electron traps. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a consistent voltage is output for a plurality of currents.

Abstract: In order to reduce slew rate and minimize delay skew, the invention adds a pull-down booster circuit connected to the gate of the driving transistor and/or a pull-up booster circuit connected the gate of the driving transistor. The pull-down booster circuit is adapted to dynamically pull-down the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from a first voltage (e.g., a logical “0”) to a second voltage (e.g., a logical “1”). The pull-up booster circuit is adapted to dynamically pull-up the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from the second voltage to the first voltage.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers the full width of the device and takes current out of the source in a primarily vertical direction.

Abstract: A ring oscillator (and test circuit incorporating the ring oscillator and test method therefor) includes an odd number of elements interconnected in a serially-connected infinite loop, each oscillator element having an associated programmable delay feature. The circuit can be used to measure effects of Negative Bias Temperature Instability (NBTI) in p-channel MOSFETs (PFETs).

Abstract: An integrated switch fabric architecture comprises: a plurality of high speed SERializer/DESerializer (SERDES) transceiver devices adapted for operation in an Inter-Cabinet, Cabled environment (SERDES ICC-type) and, a plurality of high speed SERDES transceiver devices adapted for operation in a High Speed Backplane (HSB) environment (SERDES HSB-type) that are maximally integrated on a single IC chip die to form a modular switch element for enabling communication among nodes of a network. The switch fabric architecture includes a crossbar switch device for communicating with a communications link associated with each ICC SERDES transceiver device and HSB SERDES transceiver device for enabling communication between the links inside the modular switch element.

Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.

Abstract: A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.

Abstract: A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.

Abstract: An elastic-type first-in-first-out (FIFO) buffer network for an input/output interface to enable higher link layer clock frequencies given fixed transmit clock frequencies of these “parallel-serial” high speed link interfaces. The network is particularly applicable to interface components used in InfiniBand type hardware.

Abstract: A variable-frequency digital ring oscillator provides small and consistent frequency adjustments throughout a locked range. The ring oscillator of the invention is standard cell placeable and operates at the technology limits to provide small and precise delay changes that is inexpensive to implement. The digital variable-frequency ring oscillator includes multiple macro delay elements forming an inverter ring circuit, each element having an individual macro delay unit that in turn is comprised of multiple adjustable delay units. All of these adjustable delay units are controlled by a single delay control signal.

Abstract: A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers the full width of the device and takes current out of the source in a primarily vertical direction.

Abstract: A method and device for A pass transistor device which includes a source; a drain opposite the source, a body between the source and the drain, and a circuit control network connected between the drain and the source, wherein the circuit control network controls a potential voltage of the body and provides overvoltage protection to the pass transistor.

Abstract: In parallel-serial architecture based networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data links so that data transmission occurs at the same time in the receive path of the I/O “processor.” The processor can be an I/O device for a host channel adapter, a target channel adapter, or an interconnect switch in an InfiniBand-type network.

Abstract: A flash analog to digital converter includes a reference ladder, consisting primarily of resistors, a plurality of comparators, each coupled to a different reference voltage on the reference ladder (the comparators compare a received voltage with a reference voltage level developed across corresponding resistor or group of resistors), and a variable power source coupled to the reference ladder for varying the reference levels generated from the ladder. The structure includes a fixed (or variable) gain driver supplying the received signal voltage to the bank of comparators. The variable power source can be an adjustable current source or an adjustable voltage source. The comparators can be single-ended comparators or differential comparators.

Abstract: A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.

Abstract: A method and system for creating a worst case scenario model for a given integrated circuit. The method comprises the steps of sorting skew parameters of each device into groups; and assigning a positive or negative value for each one of the groups to represent the effect of the corresponding skew parameters on the functionality of the integrated circuit. The preferred embodiment of the invention provides some of the benefits of both conventional corner simulation and Monte Carlo simulation. This approach can be implemented with only a few additional simulation iterations, which mitigates the disadvantage of Monte Carlo simulations requiring many simulation iterations. Also, this approach allows a greater degree of flexibility with respect to determining a specific corner file definition, allowing the designer to explore a greater area of model parameter space to insure that the circuit will meet performance requirements over extremes of process technology variation.

Abstract: A method and structure for calibrating an analog to digital converter comprises an input signal; a driver receiving the input signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2n−1 digital outputs; an encoding logic unit encoding the comparison result into n digital bits as an output signal; a calibration engine outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit receives the reference adjust signal, wherein the calibration engine receives n digital bits, and controls an operation of the driver or flash circuit based on the output signal.

Abstract: A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.

Abstract: An SCSI circuit which allows for the independent control of driver slew rate and amplitude with a linear shaped driver output voltage. The circuit comprises 1) a symmetrical H-Driver having at least four predrive controls; and 2) a predrive control circuit coupled to one of the predrive controls for independently varying the amplitude and rise time. The SCSI circuit is designed to utilize minimal space on the IO circuit pad, thereby conserving the amount of space allotted by the silicon area on the integrated circuit chip.