Patents Represented by Attorney, Agent or Law Firm Richard J. Botos
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Patent number: 6380083Abstract: A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. A barrier layer to prevent copper diffusion is then deposited over the entire surface of the substrate. A dual copper layer is formed on the barrier layer. The dual layer has a copper layer deposited by PVD and a copper layer deposited by electroplating. The copper layers are adjacent to each other. The ratio of the thickness (X) of the electroplated, layer to the thickness of the PVD layer (Y) is about 1:0.5 to about 1:2. The thickness of the electroplated layer is at least about 3 &mgr;m. The thickness of the PVD copper layer is at least about 100 nm. The thickness of the two layers is selected to effect recrystallization of the electroplated copper from a small grain size (0.1 &mgr;m to 0.2 &mgr;m) to a large grain size (1 &mgr;m or greater).Type: GrantFiled: May 10, 2000Date of Patent: April 30, 2002Assignee: Agere Systems Guardian Corp.Inventor: Michal Edith Gross
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Patent number: 6368753Abstract: A method for repairing scalpel masks is described. In particular, opaque defects are repaired by milling with a gallium beam at a sufficient energy to ensure appropriate implantation of gallium into the membrane underlying the blocking material. Transparent defects are repaired using a gallium beam that impacts styrene gas in the vicinity of the defect to be repaired.Type: GrantFiled: August 27, 1999Date of Patent: April 9, 2002Assignee: Agere Systems Guardian Corp.Inventors: Lloyd Richard Harriott, Anthony Edward Novembre
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Patent number: 6370307Abstract: An optical device that is a waveguide with a heating element thereon that is formed on a silicon substrate is disclosed. The waveguide is formed on a region of porous silicon formed in the silicon substrate. The porous silicon region provides greater resistance to the flow of heat than the silicon substrate on which the device is formed. Optionally, the porous silicon region also provides greater resistance to the flow of heat than the waveguide.Type: GrantFiled: July 15, 1999Date of Patent: April 9, 2002Assignee: Agere Systems Guardian Corp.Inventors: Allan James Bruce, Alexei Glebov, Joseph Shmulovich, Ya-Hong Xie
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Patent number: 6366414Abstract: An electro-mechanical structure which controls the movement of an optical device coupled thereto is disclosed. Both the electro-mechanical structure and the optical device are disposed on a substrate surface. The electro-mechanical structure controls the movement of the optical device by first lifting the optical device a predetermined distance above the plane of the substrate surface. Thereafter, the lifted optical device is moveable relative to the plane of the substrate surface in response to an electrostatic field generated between the electro-mechanical structure and the substrate.Type: GrantFiled: September 3, 1999Date of Patent: April 2, 2002Assignees: Agere Systems Guardian Corp., Lucent Technologies Inc.Inventors: Vladimir Anatolyevich Aksyuk, David John Bishop
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Patent number: 6353911Abstract: A method and apparatus for iteratively decoding a multilevel modulated signal in which the soft output information of a channel decoder is fed back and utilized by a tailored soft demapping device in order to improve the decoding result by further iterative decoding steps. The receiver includes a demapper for generating a demapped signal, bit deinterleaver for generating a demapped and deinterleaved signal and a decoder for generating soft reliability values representative of the decoded signal. These soft reliability values are then bit interleaved and fed back to the demapper, as a priori knowledge, for use in further iterations of the decoding process.Type: GrantFiled: April 2, 1999Date of Patent: March 5, 2002Assignee: Agere Systems Guardian Corp.Inventor: Stephan Ten Brink
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Patent number: 6350659Abstract: A process for fabricating a silicon-on-insulator integrated circuit in conjunction with a process for shallow trench isolation is disclosed. The shallow trench isolation is performed to define active regions in the silicon substrate. The active regions are electrically isolated from each other by regions of silicon dioxide formed in the substrate by the shallow trench isolation process. The height of the silicon dioxide regions above the substrate surface defines the combined thickness of the islands of silicon dioxide and the silicon formed over the islands of silicon dioxide. A mask is then formed on the silicon substrate with the regions of silicon dioxide formed therein. The mask defines the regions on the silicon substrate surface on which the islands of silicon dioxide are to be formed. The silicon dioxide islands are formed with the mask in place, and the mask is subsequently removed. Single crystal silicon is formed epitaxially on the structure.Type: GrantFiled: September 1, 1999Date of Patent: February 26, 2002Assignee: Agere Systems Guardian Corp.Inventors: Chun-Ting Liu, Chien-Shing Pai
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Patent number: 6312581Abstract: A process for fabricating a silica-based optical device on a silicon substrate is disclosed. The device has a cladding formed in a silicon substrate. The device also has an active region, and that active region is formed on the cladding. The cladding is fabricated by forming a region of porous silicon in the silicon substrate. The porous silicon is then oxidized and densified. After densification, the active region of the device is formed on the cladding.Type: GrantFiled: November 30, 1999Date of Patent: November 6, 2001Assignee: Agere Systems Optoelectronics Guardian Corp.Inventors: Allan James Bruce, Alexei Glebov, Joseph Shmulovich, Ya-Hong Xie
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Patent number: 6300156Abstract: A process for fabricating a MEMS device is disclosed. The device has at least one hinged element. The MEMS device including the hinged element is delineated and defined on a semiconductor substrate. The substrate is placed device side down in a chamber. The MEMS device is then exposed to a release expedient for sufficient amount of time for the release expedient to dissolve a sacrificial material connecting the element to the substrate. Upon the dissolution of the sacrificial material, the element is released from the substrate and pivots away from the surface.Type: GrantFiled: April 7, 2000Date of Patent: October 9, 2001Assignees: Agere Systems Optoelectronics Guardian Corp., Lucent Technologies Inc.Inventors: Robert LeRoy Decker, Valerie Jeanne Kuck, Mark Anthony Paczkowski, Peter Gerald Simpkins
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Patent number: 6297154Abstract: A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. At least one recess is formed in the layer of dielectric material. Barrier layers and seed layers for electroplating are then deposited over the entire surface of the substrate. The recess is then filled with copper by electroplating copper over the surface of the substrate. The electroplated copper has an average grain size of about 0.1 &mgr;m to about 0.2 &mgr;m immediately after deposition. The substrate is then annealed to increase the grain size of the copper and to provide a grain structure that is stable over time at ambient conditions and during subsequent processing. After annealing, the average grain size of the copper is at least about 1 &mgr;m in at least one dimension. The copper that is electroplated on the dielectric layer is then removed using an expedient such as chemical mechanical polishing.Type: GrantFiled: August 28, 1998Date of Patent: October 2, 2001Assignee: Agere System Guardian Corp.Inventors: Michal Edith Gross, Christoph Lingk
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Patent number: 6296984Abstract: A process for device fabrication and resist materials that are used in the process are disclosed. The resist material contains acid labile groups either pendant to the polymer or to a dissolution inhibitor that is combined with the polymer. The acid labile groups significantly decrease the solubility of the polymer in a solution of aqueous base. The resist material also contains a photoacid generator and a radical scavenger. The radical scavenger reduces the amount of aromatic compounds outgassed from the resist during the lithographic process. A film of the resist material is formed on a substrate and exposed to delineating radiation. The radiation induces a chemical change in the resist material rendering the exposed resist material substantially more soluble in aqueous base solution than the unexposed portion of the resist material. The image introduced into the resist material is developed using conventional techniques, and the resulting pattern is then transferred into the underlying substrate.Type: GrantFiled: March 12, 1999Date of Patent: October 2, 2001Assignees: Agere Systems Guardian Corp., Arch Specialty Chemicals, Inc.Inventors: Allen H. Gabor, Francis Michael Houlihan, Omkaram Nalamasu
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Patent number: 6292384Abstract: A high density read only memory structure is arranged to have the decoders and selectors which are used to access the read only memory arrays in a layer which is above and/or below the read only memory array layers. Note that by layer it is meant a substantially planar structure with some thickness in which the circuitry that makes up particular functionality resides. Thus, the inefficient two-dimensional structure of the prior art is folded over to create a compact read only memory device with a three-dimensional structure. Connection of the decoders to the rows is not limited to the ends of the rows, but instead may be made at any point along the rows. Similarly, connection of the selectors to the columns is not limited to the ends of the columns, but instead may be made at any point along the columns. Advantageously, additional circuitry is not required on the periphery of the memory array, so that a smaller overall memory device is achieved.Type: GrantFiled: June 5, 2000Date of Patent: September 18, 2001Assignee: Agere Systems Guardian Corp.Inventor: Jay Henry O'Neill
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Patent number: 6264749Abstract: The present invention is directed to a process for forming composite films. The films are formed on a substrate by directing a gas containing reactant species onto the substrate. The composite film is formed from an interaction between two reactant species. At least a portion of the substrate remains within the purview of the plasma discharge while the composite film is formed on the substrate.Type: GrantFiled: June 15, 1999Date of Patent: July 24, 2001Assignee: Agere Systems Guardian Corp.Inventors: Anthony Michael DeSantolo, Mary Louise Mandich
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Patent number: 6265239Abstract: A method for pivoting an optical device about one or more axes thereof is disclosed. Springs couple the optical device to the micro-electro-mechanical structure. A portion of the springs are fastened on the micro-electro-mechanical structure. Fastening the portion of each spring on the electromechanical structure prevents the springs from moving the optical device in a translational direction when such optical device pivots about the one or more axes.Type: GrantFiled: September 3, 1999Date of Patent: July 24, 2001Assignees: Agere Systems Optoelectronics Guardian Corp., Lucent Technologies IncInventors: Vladimir Anatolyevich Aksyuk, David John Bishop
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Patent number: 6261857Abstract: A process for fabricating a waveguide with a desired tapered profile is disclosed. The waveguide has a first section with a first height and a second section with a second height. The first height is greater than the second height. The waveguide height tapers from the first height to the second height. The waveguide is a compound semiconductor material and is formed using selective area growth. In selective area growth, a dielectric mask is formed on a substrate. The dimensions of the dielectric mask are selected to provide a waveguide with the desired dimensions. The compound semiconductor material is deposited on the substrate using chemical vapor deposition. The dielectric mask affects the rate at which the compound material is deposited in areas of the substrate proximate to the mask. Therefore, the profile of the waveguide formed using the selected mask dimensions is modeled and compared with the desired profile.Type: GrantFiled: June 17, 1998Date of Patent: July 17, 2001Assignee: Agere Systems Optoelectronics Guardian Corp.Inventors: Muhammad Ashrafal Alam, Mark S. Hybertsen, Roosevelt People
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Patent number: 6252253Abstract: An LED device that emits light in a pattern is disclosed. The LED device is a layer of active material that is sandwiched between a transparent substrate with an anode formed thereon and a cathode. The active material has a layer of light emitting material that emits light when electron/hole recombination is induced in the material. The patterned emission is defined by a patterned layer in the active material of the LED device. The patterned layer has at least a first thickness and a second thickness. When the device is on, the portion of the device associated with the first thickness of the patterned layer is visually distinct from the portion of the device that is associated with the second thickness of the patterned layer.Type: GrantFiled: June 10, 1998Date of Patent: June 26, 2001Assignee: Agere Systems Optoelectronics Guardian Corp.Inventors: Zhenan Bao, John A. Rogers
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Patent number: 6249075Abstract: A micro-machined transducer having a structure in which an acoustic enclosure is formed on a substrate above the plane of the substrate surface is disclosed. Forming the acoustic enclosure on the substrate above the plane of the substrate surface, rather than an acoustic cavity in a surface of the substrate, provides an acoustic cavity whose size is not limited by the thickness of the substrate.Type: GrantFiled: November 18, 1999Date of Patent: June 19, 2001Assignees: Lucent Technologies Inc., Agere SystemsInventors: David John Bishop, Robert Albert Boie, Flavio Pardo
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Patent number: 6218057Abstract: A lithographic process for making an article such as a semiconductor device or a lithographic mask is disclosed. In the process, articles are fabricated by a sequence of steps in which materials are deposited on a substrate and patterned. These patterned layers are used to form devices on the semiconductor substrate. The desired pattern is formed by introducing an image of a first pattern in a layer of energy sensitive material. The image is then developed to form a first pattern. A layer of energy sensitive material is then formed over the first pattern. An image of a second pattern is then formed in the layer of energy sensitive material formed over the first pattern. The second pattern is then developed. The desired pattern is then developed from the first pattern and the second pattern.Type: GrantFiled: April 16, 1999Date of Patent: April 17, 2001Assignee: Lucent Technologies Inc.Inventors: Raymond Andrew Cirelli, Omkaram Nalamasu, Stanley Pau, George Patrick Watson
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Patent number: 6211539Abstract: It has been found that through the use of ferrocene or iron pentacarbonyl based compounds, it is possible to produce semi-insulating epitaxial layers of indium phosphide-based compounds by an MOCVD process. Resistivities up to 1×109 ohm-cm have been achieved as compared to resistivities on the order of 5×103 ohm-cm for other types of semi-insulating epitaxial indium phosphide.Type: GrantFiled: February 22, 1994Date of Patent: April 3, 2001Assignee: Lucent Technologies Inc.Inventors: Wilbur Dexter Johnston, Jr., Judith Ann Long
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Patent number: 6201631Abstract: An electro-optic device which includes a mirror array attached to a base substrate is disclosed. The mirror array comprises a substrate having a plurality of spaced-apart mirrors with underlying cavities (each having a diameter at least about the same size as that of the overlying mirror) formed therein. The base substrate includes a plurality of electrodes as well as a plurality of electrical interconnections. The mirror array is attached to the base substrate so that each mirror of the array as well as a cavity are supported above a set of electrodes. Each mirror of the mirror array rotates relative to the major plane of the substrate in response to an electrical signal. The application of an electrical potential to each mirror relative to at least one electrode of the set of electrodes causes the desired rotation (depending on the magnitude of the electrical potential) up to an angle of about 20 degrees.Type: GrantFiled: April 26, 2000Date of Patent: March 13, 2001Assignee: Lucent Technologies Inc.Inventor: Dennis Stanley Greywall
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Patent number: 6197641Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers.Type: GrantFiled: June 18, 1999Date of Patent: March 6, 2001Assignee: Lucent Technologies Inc.Inventors: John Michael Hergenrother, Donald Paul Monroe, Gary Robert Weber