Abstract: An integrated circuit chip comprises a digital signal processor core (12) formed on a portion of the surface area of the chip (10). The digital signal processor (12) has a read only memory (14), a random access memory (16), a register file (18), an arithmetic logic unit (20) and a multiplier circuit (22). The remaining surface area of the integrated circuit chip (10) forms a user-definable circuitry area (24) which is used to form added circuitry to interface the digital signal processor (12) with other components of an integrated data processing system. The circuits formed in the user-definable circuitry area (24) are coupled to other integrated circuit chips through universal input/output bond pads (28). In one embodiment of the present invention, parallel module testing multiplexers (26) are added to aid in the testing of the digital signal processor (12) and the added circuits formed in the user-definable circuitry area (24).

Abstract: A method for a wafer cleaner using a rotation mechanism. Wafers are placed into a carrier 3 having grooves to maintain a spacing between the wafers. The carrier 3 and wafers are placed into a tank 1 with a cleaning solution. Nozzles 11 are used to direct pressurized solution against the wafers causing them to rotate within the carrier. In another embodiment, the tank 1 includes a megasonic transducer 16. In the second embodiment, the wafers are rotated while the megasonic transducer 16 is producing megasonic energy. The rotation of the wafers causes the cleaning solution and the megasonic energy to act on the wafers uniformly, and further exposes the edges of the wafers directly to the cleaning solution and the megasonic energy, thereby enhancing particle removal from the wafers. Other embodiments are provided.