Abstract: A method of constructing opto-electronic integrated circuit packages passively aligns optical fibers inserted through holes in a package lid which are arranged in a pattern which corresponds with the pattern of emitters and receivers on a circuit die. When the lid is aligned with a package base to which the die is attached at a predetermined location, the fibers simultaneously couple to the emitters and receivers. The package components are each formed with alignment indicators. To assemble the packages, the alignment indicators are optically aligned to orient the components properly and the components are positioned such that centers of particular indicators are in predetermined positions relative to the centers other indicators. The components are then held in position while an affixation process secures them in place. Before the lid is secured to the base, a laser drills optic fiber holes to precise sizes in an array which corresponds with the locations of emitters and receivers on the die.

Abstract: A distributed digital data processing system including a host and at least one node interconnected by a communications link. In response to a boot command, the node requests its boot image from the host over the communications link. The host then provides pointers to portions of the boot image to the node. The node then retrieves the portions of the boot image identified by the pointers. These operations are repeated until node retrieves the entire boot image. By having the host supply pointers to the boot image and the node perform the retrieval operations in response to the pointers, the host is freed to perform other operations while the node is actually performing the retrieval operations.

Abstract: A method for static analysis of a software model of a circuit clocked by two clocks where the two clocks' periods are multiples of a greatest common divisor period. In the invention, a composite clock is determined with a period equal to the least common multiple of the periods of the two clocks, and the model is statically analyzed relative to the composite clock.

Abstract: A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled.

Abstract: A bridge-type primary switching circuit (12) is represented by a pulsed voltage source (VSW). The primary switched waveform is transformed to secondary circuit (14) using a transformer (T1) with the required turns ratio N and a center-tapped secondary winding (16). Half-bridge rectifier (18) formed by diodes (DR1) and (DR2) rectifies the secondary waveform and feeds the waveform through a low-pass filter (LF) and (CF) to obtain the desired DC output voltage. The snubber circuit (20) is represented by switch-diode-capacitor combinations (SA-DS1-CS1) and (SB-DS2-CS2) across each rectifier (DR1) and (DR2). Capacitances (CS1) and (CS2) are selected large enough such that their voltages remain essentially constant during a switching cycle. The controlled switches (SA) and (SB) are turned ON with a specific delay after the primary voltage reaches a magnitude close to the input voltage in order to allow the rectifier diodes (DR1) and (DR2) to be commutated.

Abstract: In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache.

Abstract: A system and method of satisfying read and write requests is used in a system having a plurality of cache-equipped processors coupled into a hypercube structure via buses, where each processor is simultaneously coupled to other processors on other buses via gateway means. Read and write requests for a line of data from any of the processors are satisfied by forwarding an update or invalidate request for a given data block containing the line of data requested. This request is forwarded to all other buses on which the block is present. The present invention provides for responding to a read request for a line of data from a processor by forwarding the request, and resultant data, to one of the buses on which the block is stored, where each gateway responds to the request to forward the request along exactly one branch.

Abstract: A floating point multiply of two n-bit operands creams a 2n-bit result, but ordinarily only n-bit precision is needed, so rounding is performed. Some rounding algorithms require the knowledge of the presence of any "1" in the n-2 low-order bits of the 2n-bit result. The presence of such a "1", indicates the so-called "sticky bit" is set. The sticky bit is calculated in a path separate from the multiply operation, so the n-2 least significant sums need not be calculated. This saves time and circuitry in an array multiplier, for example. In an example method, the difference between n and the number of trailing zeros, "x", in one of the n-bit operands is detected, by transposing the operand and detecting the leading one. The other operand is right-shifted by a number of bit positions equal to this difference. A sticky bit is generated if any logic "1's" are in the low-order n-x-2 bits fight shifted out of the second operand.

Abstract: A lockout avoidance circuit is provided for a plurality of nodes which generate lock requests for a shared resource such as a memory location. The circuit insures that lock requests are eventually satisfied. A lock queue includes a plurality of registers pipelined together. Lock requests only enter the lock queue if they are refused access to a shared resource a predetermined number of times. A first register is the head of the queue and the last register is the bottom of the queue. An enabling circuit allows the queue to store in the registers lock requests received from the different nodes in the order in which they are initially refused service. The enabling circuit operates the queue by pushing the stored lock requests toward the head of the queue each time the head entry in the queue is serviced. The lockout avoidance circuit is implemented at each level of the system wherein a lockout condition can occur.

Abstract: A transient voltage suppression circuit consists of energy dissipation components with one end connected either to a line or a neutral wire of a power line and the other end connected to a reed switch which, in turn, is connected to ground. The reed switch, which is an encapsulated switch consisting of two metal strips with a gap between them, is in an open position, and accordingly, does not under normal operating conditions provide a path to ground for the associated energy dissipation components. The energy dissipation components thus do not conduct. When a transient having a sufficiently high voltage occurs between the line or neutral wires and the ground wire, it causes the reed switch to conduct momentarily, that is, spark, across the gap. The switch momentarily forms a path to ground and allows the associated energy dissipation components to shunt a transient current away from protected appliances.

Abstract: A card cage formed of mating, identical halves provides parallel slots for circuit boards carrying snap-on retainer clips with integral pawl-like clasps which lock over ridges on the exterior of the card cage. The clip is released from the cage by squeezing the clasps with one hand before withdrawing the circuit board. Slotted side brackets capture mating ribs on the card cage halves to assemble and mount the card cge to a wiring clost panel.

Abstract: A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

Abstract: A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.

Abstract: A circuit is provided for using the input operands of a floating point addition or subtraction operation to detect the leading one or zero bit position in parallel with the arithmetic operation. This allows the alignment to be performed on the available result in the next cycle of the floating point operation and results in a significant performance advantage. The leading I/O detection is decoupled from the adder that is computing the result in parallel, eliminating the need for special circuitry to compute a carry-dependent adjustment signal. The single-bit fraction overflow that can result from leading I/O misprediction is corrected with existing circuitry during a later stage of computation.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

Abstract: A desktop communications network connects numerous peripheral devices to a host computer via a single host interface. The host interface and each peripheral device's interface has its own CPU, with software for assigning each peripheral device a unique address. The bus interface associated with each peripheral device typically stores a unique identifier string that is used by the host computer to identify each peripheral device connected to the network. Alternately, the host can distinguish identical peripheral devices by the order in which they are first used. As a result, several peripheral devices of the same type can be connected to the network, each being assigned a distinct network address. Peripherals can be connected and disconnected to the desktop bus while the system is running. The software in the host and peripheral bus interfaces automatically reconfigure the assigned bus addresses.

Abstract: In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the origin of desired destination area in destination memory to the requested position in the destination area. A plurality of drawing graphics commands specify different raster drawing operations. A plurality of context graphics commands is used to define a desired context in which drawing graphics commands operate. The defined context includes destination location for resulting data, type and plane depth of graphics operations, foreground and/or background color of resulting data. Different parts of the context are changeable/redefinable independently of the other parts.

Abstract: A driver circuit employs an N-channel pull-down transistor of relatively small size, directly connecting an output node to ground, and another path consisting of a pair of series-connected N-channel transistors connecting the node to ground; the lower of these is driven by the logic voltage which is applied to the gate of the pull-down, and the other has its gate connected to the output node. Two parallel discharge paths are thus provided for the output node, one through the small pull-down transistor, and a second through the (larger) series transistors. When a returning wave from the output node (due to transmission line effects) hits the driver circuit, the series transistors turn off, but the pull-down transistor is still on keeping the driver output node at a valid "low." In cases of mismatch or noise, the pull-down transistor will help absorb refections or ringing.

Abstract: A method and apparatus for controlling accesses to main memory by a CPU includes a CPU coupled to the main memory by a first switching device. A system bus is coupled to main memory by a second switching device. The system bus couples a plurality of functional units to main memory. The first and second switching devices are interconnected so that only one of the two switching mechanisms can release the connection between the CPU or the system bus and the main memory. Advantageously, a first buffer is coupled between the main memory and the CPU for temporary storage of data which is to be transferred between the CPU and main memory, and a second buffer is coupled between main memory and the system bus for temporary storage of data which is to be transferred between the system bus and main memory. The main memory, the first and second switching mechanisms as well as the first and second buffers are provided on the same board as the CPU.