Abstract: A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.

Abstract: A method and system for efficient allocation of limited manufacturing resources over time to meet customer demand. At the enterprise planning level this typically requires determination of a feasible production schedule for an extended supply chain. The method and system utilizes a new and unique type of systematic decomposition based on both product and process considerations. This approach simultaneously reduces the model size (and therefore computation time) and increases modeling flexibility from strictly linear programming based decision making to include more general nonlinear programming characteristics.

Abstract: The current invention performs short pulse laser ablation of clear defect regions on a mask prior to patching the clear defect regions. The short-pulse laser ablation removes any residue that absorbs light. Thus, the ablation completely cleans the surface of the clear defect regions, meaning that any patches of the surface will better adhere to the surface of the mask. This is particularly important during those situations where a later etch of a conductive surface added to the mask creates a solvent because the etchant interacts with residue on the mask, and wherein the solvent attacks the patch material at the patch material's interface.

Abstract: An integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the capacitor includes a first insulator layer overlying an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are provided in the first insulator layer and are separated by a trench defined by the first insulator layer and by sidewalls of the first and second conductive lines. A first conductive barrier layer overlies and connects the first and second conductive lines, and a second insulator layer overlies the first conductive barrier layer. A second conductive barrier layer overlies the second insulator layer, and a third conductive line is disposed in the trench and overlies the second conductive barrier layer.

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.