Abstract: A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI.

Abstract: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

Abstract: A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.

Abstract: A method and system for efficient allocation of limited manufacturing resources over time to meet customer demand. At the enterprise planning level this typically requires determination of a feasible production schedule for an extended supply chain. The method and system utilizes a new and unique type of systematic decomposition based on both product and process considerations. This approach simultaneously reduces the model size (and therefore computation time) and increases modeling flexibility from strictly linear programming based decision making to include more general nonlinear programming characteristics.

Abstract: The current invention performs short pulse laser ablation of clear defect regions on a mask prior to patching the clear defect regions. The short-pulse laser ablation removes any residue that absorbs light. Thus, the ablation completely cleans the surface of the clear defect regions, meaning that any patches of the surface will better adhere to the surface of the mask. This is particularly important during those situations where a later etch of a conductive surface added to the mask creates a solvent because the etchant interacts with residue on the mask, and wherein the solvent attacks the patch material at the patch material's interface.

Abstract: A computer implemented Availability Checking Tool enabling tool users to execute within a common work environment, from common enterprise data, and considering assets and demands across multiple order management systems and manufacturing facilities within boundaries established by manufacturing specifications and process flows and business policies. The tool receives orders from multiple demand sources or ordering systems. Tool users can easily maintain a synergistic relationship between multiple ordering systems. A demand configurator coordinates product requests based on information from the demand source according to certain rules and priorities assigned to the product requests. A material resource engine manipulates data from the demand configurator and the rules to provide material supply information. A solver manipulates the material supply information from the resource engine and the rules to provide optimized product availability information.

Abstract: An integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the capacitor includes a first insulator layer overlying an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are provided in the first insulator layer and are separated by a trench defined by the first insulator layer and by sidewalls of the first and second conductive lines. A first conductive barrier layer overlies and connects the first and second conductive lines, and a second insulator layer overlies the first conductive barrier layer. A second conductive barrier layer overlies the second insulator layer, and a third conductive line is disposed in the trench and overlies the second conductive barrier layer.

Abstract: A method of, computer system for, and computer program product for causally relating costs to products comprises, identifying resource costs for manufacturing the product, computing load factors for each of the resource costs, producing weighted resource costs based on the resource costs and the load factors, summing the weighted resource costs for the product, determining a volume of the product manufactured, and dividing the weighted resource costs by the volume to produce a weighted cost per product.

Abstract: A method of, computer system for, and computer program product for causally relating costs to products, including relating costs to a wafer having semiconductor chips comprising identifying resource costs for manufacturing the wafer including identifying equipment costs, computing load factors for each of the resource costs (the computing load factors for the equipment costs comprising determining a number of exposure fields on the wafer, computing a raw processing time for the wafer based on the number of exposure fields, and determining a percentage the raw processing time represents of a manufacturing time period on an equipment element, the equipment element having the equipment costs), producing weighted resource costs based on the resource costs and the load factors, (the producing weighted resource costs for the equipment costs comprising multiplying the equipment costs by the percentage), summing the weighted resource costs for the wafer, determining a volume of the wafer manufactured, and dividing th

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.