Abstract: In a sense amplifier for reading out memory cells of a memory comprising a set of P-FETs and N-FETs, complementary input signals received from the memory cell being read out are applied to input junctions connected to gates of N-FETs. The input junctions are charged to 0.8 volts by a precharging circuit comprising P-FETs connecting the input junctions to ground and an N-FET shunting the input junctions together. The P-FETs and N-FETs of the precharging circuit are rendered conductive between memory cells readouts to precharge the input junctions and are rendered nonconducting during memory cell readouts. A second precharging circuit precharges an output junction of the sense amplifier circuit. The output junction is connected to an output amplification stage including a CMOS circuit. Because of the low equalization voltage to which the input junctions are precharged, the time to precharge the input junctions is dramatically reduced and a reduction in the memory access time is achieved.

Abstract: A sealing mechanism comprises a support member forming part of the semiconductor producing apparatus which has a vacuum chamber, a rotation shaft rotatably received in the support member, and at least three seal rings axially spaced apart from each other between the support member and the rotation shaft to form a first fluid chamber close to the atmosphere and a second fluid chamber close to the vacuum chamber. The first fluid chamber is vacuumized to have a first pressure, and the second fluid chamber is also vacuumized to have a second pressure which is lower than the first pressure. The first and second fluid chambers work together to enhance the sealing performance of the sealing mechanism.

Abstract: In a radio remote blasting system, a radio receiver triggers a blocking oscillator which generates a high voltage output. A rectifier rectifies the high voltage output and charges a capacitor, which is coupled to a plasma arc generator to apply the capacitor voltage to the plasma arc generator and generate a high voltage arc in the arc generator. The end of a shock tube is received in a port in the arc generator and the arc produced in the arc generator will ignite explosive material in the shock tube. The resulting explosion will travel from the point of ignition to an explosive device which will then be detonated.

Abstract: An electromagnetic force motor comprising: a magnetic housing having a housing chamber formed therein; a stationary magnetic member received in the housing chamber in stationary relationship with respect to the magnetic housing; a movable magnetic member received in the housing chamber to be movable with respect to the stationary magnetic member, the stationary magnetic member, and the movable magnetic member forming with a magnetic flux gap to permit a magnetic flux to pass therethrough, the magnetic housing, the stationary magnetic member, and the movable magnetic member each made of a magnetic substance and collectively forming a magnetic circuit unit that is to allow a magnetic flux to pass therethrough; a permanent magnet positioned in the housing chamber and generating a magnetic flux; and an electromagnetic coil positioned in the housing chamber and generating a magnetic flux with an electric current imparted thereto, the magnetic circuit unit partly having a diminished cross-sectional area being small

Abstract: In a coin operated amusement game, a coin track is provided directing coins toward a plurality of target receptacles arranged to receive properly timed coins. Relative movement is provided between the target track and the receptacles. A properly timed coin inserted in the track will roll down the track, then travel through the air, and then land in and be retained in the target receptacle. Dump targets are provided wherein a properly timed coin will activate the dump target and cause the corresponding receptacle to be dumped and provide the player with an award corresponding to the number of coins dumped out of the receptacle.

Abstract: In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a line in said cache memory, the bin number and line position identification of the line in the cache memory are saved in a continuation register. Then, subsequently, when data is fetched from the same line, it is fetched by a continuation request wherein the data saved in the continuation register is used to access the cache memory. The continuation registers provide the abbreviated address data for comparison in both PSC (program store compare) and OSC (operand store compare).

Abstract: Generation of functional status followed by the use of the status to control the sequencing of microinstructions is a well known critical path in processor designs. The delay associated with the path is exacerbated in superscalar machines by the additional statuses that are produced by multiple functional units from which the appropriate status must be selected for controlling the sequencing of microinstructions. This is especially true in horizontally microcoded machines. The adverse affects on the delay can be reduced by using a staged multiplexor design. For the staged multiplexor to be useful, all functional unit status should be produced as early as possible. In this invention, a status predictor is described that allows the status associated with the shifter to be generated directly from the inputs to the shifter.

Abstract: A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level.

Abstract: A central time-of-day reference is integrated into a switch which interconnects I/O devices and host processors in a computer complex via fiber-optic links. A time reference oscillator in the switch serves to generate incrementing reference signals for the central reference and also provides a clock signal for the switch transmissions. Units to which the switch is attached obtain clock signals from their regenerated clocks which are synchronized to the time reference oscillator, and use the regenerated clock signals to control their local time-of-day references. Each unit periodically transmits a signal to the switch requesting a dynamic connection to the switch-based central time-of-day reference in order to receive a time of day message.

Abstract: An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage.

Abstract: This is a method of compounding two or more instructions from an instruction stream without knowing the starting point or length of each individual instruction. All instructions include one OP Code at a predetermined field location which identifies the instruction and its length. Those instructions which qualify need to have appropriate tags to indicate they are candidates for compounding. In System 370 where instructions are either 2, 4 or 6 bytes in length, the field positions for the OP Code are presumed based on an estimated instruction length code. The value of each tag based on a presumed OP Code is recorded, and the instruction length code in the presumed OP Code is used to locate a complete sequence of possible instructions. Once an actual instruction boundary is found, the corresponding correct tag values are used to identify the commencement of a compound instruction, and other incorrectly generated tags are ignored.

Abstract: A fixed roller pulverizing mill wherein there is comparatively little wear, vibration or other adverse characteristics and wherein a uniform fineness of the ground material is maintained. The rollers, which do not move substantially in a horizontal direction, bear down on a rotating table, contacting the table at a circular trough therein and are individual spring biased to improve the performance of the mill.

Abstract: In an industrial process control system, in which the process is controlled via multiplicity of I/O data points communicating with a computer system controller, errors in the addressing signals selecting the I/O data points are prevented from causing the incorrect setting or reading out incorrect data from wrongly selected data points. A multibit parity signal is generated from the address signals as presented at the output of the computer controller and this parity signal is compared with a second multibit parity signal generated from the address signals as applied to the I/O racks on which the I/O data points are organized. If the parity signals don't compare, the change of the setting of or the read out of valid data from the I/O data point selected by the address signal is prevented.

Abstract: A burner monitoring system in which an array of burners are viewed by a video camera adapted to produce a video signal representing the infrared image of the burner array. The video processing electronics processes the video signal to determine which of the burners is lit and which of the burners is unlit by the presence or absence of hot spots in the infrared image. The video processing electronics generates a video signal which is applied to a cathode ray tube device to generate a visual indication for each of the burners indicating the lit or unlit condition of each of the burners.

Abstract: An electron microscope of a scanning type provided with two specimen stages for allowing specimens of a large size and a small size to be selectively and interchangeably observed. The microscope comprises an electron gun, a first objective lens for observing a small size specimen, a second objective lens for observing a large size specimen, the second objective lens being disposed in axial opposition to the electron gun with the first objective lens disposed therebetween. The specimen stage for the small size specimen is disposed in the vicinity of the first objective lens, while the specimen stage for the large size specimen is disposed near the focal plane of the second objective lens. Improved stability, high resolving power and simplified manipulatability are attained.

Abstract: A combined mode program-panel controller method for a distributed industrial process control system permits a system operator to configure the overall system architecture to control the sequential operation of the entire system or a sub-portion thereof. The program-panel controller includes a first user accessible graphic program by which the system architecture can be symbolically reconfigured and a second user accessible instruction set program by which the operating parameters of the so-configured system or a sub-portion thereof may be altered.

Abstract: An industrial process control system in accordance with the present invention includes a plurality of device controllers connected together through a common buss with each device controller connected to an associated controlled device(s) that effect process control. A computer-aided system interface for controlling the overall system includes a visual display device in the form of a multi-color CRT and a graphic input device in the form of a transparent touch-responsive panel that overlies the CRT display screen. Computer generated symbols representing the controlled devices are displayed on the CRT screen to define touch-responsive target areas. When an appropriate target area is touched by a human operator, a signal, such as a command signal, is generated to cause the controlled device whose symbol is displayed in the designated target area to respond, with this response being then indicated by a change in the device symbol being displayed on the screen.

Abstract: A control system for controlling an industrial process includes a plurality of remotely located process control units (remotes) each coupled to an associated input/output device(s) and adapted to communicate with one another through a dual channel communications link. Each remote has a unique succession number within a predetermined succession order with supervisory communication-control of the communication link sequentially transferred to each remote according to its succession number to provide a revolving or master for the moment control of the system. Each remote after completing its turn as master transmits a control block to the next remote in the sequence. Each remote, when exercising supervisory communication control of the communication link, may transmit data in block form to other remotes and request and receive data back from other remotes.