Abstract: A semiconductor package device is disclosed. In one embodiment, attached by its active face to a lead-on-chip leadframe having leadfingers is an integrated circuit. The integrated circuit has a roughened backside. An encapsulating material surrounds the integrated circuit and the lead-on-chip leadframe so that the leadfingers are exposed. The roughened backside surface helps to reduce package cracking arising from mounting the device to a printed circuit board by reflow solder.

Abstract: A substrate bias detection circuit is disclosed. The circuit includes first and second transistors, where the first transistor has its source coupled to the substrate and where the second transistor has its source coupled to a common potential (i.e., ground). The gate and drain of the first transistor are connected together, and to the gate of the second transistor. Load devices are connected between the drains of the first and second transistors and a bias potential from a power supply node. The threshold voltages of the first and second transistors may be different, with the difference determining the voltage that the substrate must reach, relative to the common potential, to cause the circuit to respond. Upon the substrate reaching a voltage sufficient to turn the second transistor on, the drain of the second transistor will be pulled toward the common potential, indicating loss of substrate bias.