Abstract: A semiconductor device assembled as a compact tape carrier package (TCP) for tape-automated bonding(TAB). An IC chip 3 has a connection surface provided with bump electrodes 15. A flexible base film 7, carrying leads 8 and having a device hole 21 smaller than the semiconductor chip's connection surface, faces the IC chip's connection surface across a small prescribed gap 22. Inner leads 8a, 8a' extending from base film 7 through device hole 21 are bonded to bump electrodes 15 on IC chip 3. To maintain gap 22 during inner lead bonding and resin sealing the chip's connection face or the base film 7 is provided with spacer projections 35 or 55 of the same length as gap 22. During inner lead bonding the spacer projections prevent base film 7 from deforming so as to dislocate inner leads 8a, 8a' from their corresponding bump electrodes. During sealing the spacer projections enable sealing resin 13 to easily flow through gap 22 to evenly coat the chip's face and sides.
Abstract: A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus.
Type:
Grant
Filed:
June 7, 1995
Date of Patent:
December 9, 1997
Assignee:
Texas Instruments Incorporated
Inventors:
Iain C. Robertson, Jeffrey L. Nye, Michael D. Asal, Graham B. Short, Richard D. Simpson, James G. Littleton
Abstract: A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
Type:
Grant
Filed:
June 7, 1995
Date of Patent:
August 12, 1997
Assignee:
Texas Instruments Incorporated
Inventors:
Gerard Benbassat, Frank L. Laczko, Sr., Stephen H. Li, Karen L. Walker, Shiu Wai Kam