Abstract: A method for implementing soft constraints in scheduling comprises receiving a description of circuit behavior. The description is un-timed. A scheduling solution is generated for use in scheduling the description. The scheduling solution includes scheduling variables and an objective function. The scheduling variables schedule the time of at least one operation. The objective function includes a penalty term and constraints comprising at least one hard constraint and at least one soft constraint. The constraints are created on the scheduling variables. The penalty term comprises a slack variable representing violations of the constraints. The penalty term measures the design cost of violating the soft constraint. Following generation of the scheduling solution, the description is scheduled by applying the scheduling solution to the description. Timing information of the description is provided as an output of the scheduling.

Abstract: An interface for communications among network elements of at least one network is provided, comprising at least one transmitter, at least one receiver, at least one processor, and at least one backplane coupled among the network elements. Data frames of a second type, or Time Slot Network (TS Net) data frames, are generated and transferred over the backplane in response to receipt data frames of a first type from the network. The TS Net data frames comprise switching event information. Compare operations are performed among prespecified TS Net data frames at prespecified intervals, and at least one interrupt signal is generated in response to data changes determined by the compare operations. Information routing is controlled over the network by a processor in response to the interrupt signal.

Abstract: A method and apparatus for generating massive interrupts in random access memory (RAM) are provided, comprising receiving and storing Time Slot network (TS Net) data frames comprising switching event information in a first RAM area. Compare operations are performed among prespecified ones of the TS Net data frames. Unit interrupt bits are set in a corresponding location of a second RAM area in response to detected bit differences resulting from the compare operations. Interrupt status bits are set in a corresponding location of a third RAM area in response to set unit interrupt bits. Massive interrupt signals are generated in response to set unit interrupt bit.