Abstract: A structure and method of designing an integrated circuit includes generating at least one device shape, altering the device shape to comply with predetermined rules, forming a first hierarchical level abstraction around the device shape (where the first hierarchical level abstraction represents a perimeter of the device shape), preparing a first hierarchical level arrangement of first hierarchical level abstractions, altering the first hierarchical level arrangement to comply with the predetermined rules, forming a second hierarchical level abstraction around the first hierarchical level arrangement (where the second hierarchical level abstraction represents a perimeter of the first hierarchical level arrangement), preparing a second hierarchical level arrangement of second hierarchical level abstractions, and altering the second hierarchical level arrangement to comply with the predetermined rules.

Abstract: A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.

Abstract: A method for using verification software for testing a system-on-chip (SOC) design including an embedded processor. The verification software is used to generate and apply test cases to stimulate the SOC design in simulation; the results are observed and used to de-bug the design. Verification of a SOC design which includes an embedded processor is typically very slow. To provide for a speed-up mode of verification in such a case, in the method of the present invention, verification software is partitioned into higher-level control code and lower-level device driver code. The higher-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations.

Abstract: A method and computer system are provided for checking integrated circuit designs for design rule violations. The method may include generating a working design data set, creating a wafer image data set, comparing the wafer image data set to the design rules to produce an error list and automatically altering the working design data set when the comparing indicates a design rule violation. The method further automatically repeats the creating, the comparing and the automatically altering until no design rule violations occur or no solution to the errors exists.

Abstract: A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two production images representing different manufacturing qualities, and comparing the production images to the design rules to produce an error list.

Abstract: A method and structure for serif mask design for correcting optical proximity effects in photolithography first characterizes a partial coherent light illumination from a photolithographic system and then utilizes the characterization results to perform serif mask design for the purpose of optical proximity corrections. The characterization of a partial coherent light illumination includes identifying an effective range of optical proximity effects for the photolithographic system, and focusing on slow-varying angle dependent terms in mutual intensity function, etc. The method and structure for serif mask design starts from ideal serif and hole design that work perfectly under a complete coherent illumination or under a complete incoherent illumination. For an outer corner, the initial design is a quarter-circle serif centered at the outer corner and located at the opposite quadrant of outer corner itself.

Abstract: A structure and method for performing optical proximity correction in photolithographic masks includes defining a hierarchy of inner bands adjacent and inside edges and ends of a mask structure within the photolithographic mask, defining a hierarchy of outer bands adjacent and outside edges and ends of said mask structure changing a transparency of part of the inner and outer bands for the mask structure to correct for optical proximity errors using predefined transparency changes, determining whether the predefined transparency changes affect the outer band of the mask structure or outer bands of other mask structures on the photolithographic mask, and altering the predefined transparency changes to prevent the predefined transparency changes from affecting the outer band and the outer bands. Domain-balancing method and algorithm are used to decide the position, shape, and size of serifs and holes in the predefined transparency changes.

Abstract: A spacing violation checker that forms conductor rectangles, forms minimum spacing rectangles, identifies possible errors and checks whether possible errors are true errors allows same net spacing errors to be recognized during physical design prior to the design rules check. The software supporting the invention performs orders of magnitude faster than the design rules check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.

Abstract: A method and structure for performing optical proximity correction in a photolithographic mask to prevent rounding of corners and line end foreshortening of a shape on the photolithographic mask comprises changing a transparency of the photolithographic mask by adding serifs and holes along each edge of the shape intersecting a comer of the shape to establish complementary symmetry along each edge of the shape, changing a transparency of quadrants around each comer of the shape to form mirror image diagonal quadrants centered on corners of the shape, reducing the size of serifs and holes by cutting out unnecessary parts to make the serifs and holes less likely to be printed and exchanging part of the serifs and holes around a comer to make the serifs and holes not printable.

Abstract: A method for blocking and/or filtering electronic mail. Selected senders are provided with a valid passcode associated with an e-mail address. When an e-mail is received at a mail server node, a field in a header of the e-mail is checked for a valid passcode associated with the destination e-mail address. If a valid passcode is detected, the e-mail is automatically sent to a receiver at the e-mail address. If an incorrect passcode is detected, the e-mail is automatically deleted at the server node and does not reach the receiver. If there is no passcode in the e-mail header, the e-mail is held temporarily, until the receiver approves to receive the e-mail. If the receiver rejects the e-mail, the e-mail is deleted. The present invention includes an additional capability for the senders of e-mails to request a passcode associated with a specific e-mail address in a lookup directory, before sending an e-mail to that address.

Abstract: A process for optimizing a manufacturing line comprises determining work center raw processing times of a plurality of work centers in the manufacturing line, summing the work center raw processing times to produce a manufacturing line raw processing time, determining work center cycle times of the work centers, dividing the work center cycle times by respective ones of the work center raw processing times to produce work center X-factors, weighting each of the work center X-factors by a percentage that a corresponding one of the work center raw processing times represents of the manufacturing line raw processing time to produce X-factor contributions for each of the work centers and modifying at least one work center of the work centers having an X-factor contribution higher than others of the X-factor contributions to reduce the X-factor contribution of the at least one work center.