Abstract: A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Abstract: Digital data bits are stored at storage locations at plural depths within a holographic medium of a holographic storage disk in the form of selective, localized alterations in a format hologram. Micro-localized regions of a reflection format hologram extending throughout the medium are deleted by focusing a high-power laser beam at desired storage locations. The deletion regions have a lower reflectivity than the surrounding parts of the format hologram. Tunable-focus storage and retrieval heads, as well as dynamic aberration compensators, are used for multi-depth access. Storage and retrieval may each be achieved with a single head.

Abstract: Disclosed is a high-speed dynamic actuating system for optical disks, particularly useful in an optical disk drive, wherein a closed-loop approach is used to overcome the diversity between devices and thus meet the requirement for high speed track-accessing and solve the problems in that the convention open-loop track-jumping takes a long period of time to perform segmental adjustment. The pick-up head is activated by applying high-speed dynamic actuation of the lens so as to conform to the pre-determined velocity curve and eliminate the wobble of the lens caused by different track-jumping times in an optical disk drive and a hard disk. In addition, said system can be implemented in an integrated circuit (IC), which is directly controlled by the hardware and thus effectively simplifies the complicated configuration as in the prior art.

Abstract: This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.

Abstract: A configurable RAM interface connecting a bus to RAM is adapted to receiving large multiword variable length tokens at a high data arrival rate, using a swing buffer and a buffer manager. An address source provides complete addresses to the interface. The buffer manager has a state machine which transitions among a plurality of states, maintaining status information about the buffers, allocating the buffers for reference by a write address generator, clearing the buffers for occupation by subsequently arriving data, and maintaining status information concerning the buffers. The buffer manager also examines tokens of received data in order to update the status of the arrival buffer.

Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: A method for converting frame data at a slower rate into field data at a faster rate in a video decoder comprises determining a basic field repetition rate such that a field is repeated an integer number of times in a frame period, calculating a ratio differential of the repetition rate by subtracting from the speed-up ratio of the faster to the slower rate, the ratio of the fields per frame period to the slower rate, comparing the ratio differential with the differential of the field repetition rate and adding or subtracting extra fields when the two are substantially at variance.

Abstract: This invention discloses a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image. The DRAM includes two separate banks, a first bank and a second bank. Each bank is capable of operating in page mode to read and write the data words. The two dimensional image is organized in a two dimensional grid pattern of cells, each cell containing an M by N matrix of pixels. The words associated with each cell occupy one page or less of a bank. Each cell is assigned a particular one of the two banks so that all data words associated with that particular cell are read from and written to one particular page of that particular bank. The assignment of banks to cells is done such that each cell is associated with a different bank than any bordering cell which is also either in the same row or in the same column.

Abstract: A plurality of processing stages interposed between an input and an output of a system including a pipeline machine interconnect for conveyance of tokens along the pipeline. Control and or data tokens in the form of universal adaptation units interface with all of the stages in the pipeline and alternatively interact with selected stages in the pipeline so that the processing stages in the pipeline are afforded enhanced flexibility in configuration and processing. In one embodiment of the system, the stages accept a data stream having portions encoded according to respectively different video formats. At least one of the stages includes circuitry for generating signals to indicate an end-of-picture data decoding. The stage includes state machine logic that is responsive to the generated signals for effecting an end of picture data decoding by clearing the pipeline.

Abstract: The present invention preferably includes a shading band which is suitably electro-optically created in a grid pattern formed through a photolithographic process, so consequently, the electro optic shading band is easily eliminated or re-configured dynamically to substantially eliminate its shading effect for lower density optical disks which do not experience substantial adjacent track crosstalk (ATC). Eliminating or reconfiguring the shading effect also helps in accommodating different media types and generations and those of different manufacturers. Moreover, the electro-optic shading band suitably adjusts the amplitude, phase, frequency, polarization and/or the like of the light beam to compensate for possible material property variations, defects, misalignments or other imperfections in the reading process. The present electro-optic shading band substantially restricts or alters any portion of a light beam containing signal information read from an optical disk.

Abstract: The present invention includes a method and apparatus for reducing the width of a mark written in optical media. When forming a long mark, the prior art recording methods typically cause blooming at the edges of the mark, resulting in a wide mark pattern which may be sensed by the read focused spot reading an adjacent track causing increased adjacent track crosstalk (ATC). However, by removing every other pulse from the write pulse waveform, the cooling sequence of the writing process is sufficiently increased to allow for additional cooling between pulses. When forming marks with less pulses, the effects of blooming are substantially reduced. Thus, because of the reduction in the effect of blooming, the problems associated with ATC, whereby adjacent track information is recorded, is substantially reduced.

Abstract: The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data.

Abstract: A method of asynchronously accessing a random access memory having a plurality of rows and columns, where each row has a wordline connected to read and write row decoders and each column is connected to bitlines. A row address is assigned to a first and second row, i.e. a pair of rows. A read address is provided to the read row decoder and a write address is provided to the write row decoder. The read and write addresses are decoded by the read and write row decoders, respectively, and one of the first or second rows is selected for reading. Asynchronous with selecting one of the first or second rows for reading, one of the first or second rows is selected for writing. Data is then read from the row selected for reading and asynchronously data is written into the row selected for writing. Signals are provided which coordinate the reading and writing of data, where in the event reading or writing is being performed, another of the reading or writing is deferred until completion of the first reading or writing.

Abstract: A pipeline structure processes data in a series of stages, each of which has a data input latch (LDIN) and passes it on to the next stage in the pipeline via a data output latch (LDOUT). The stages are preferably connected to two non-overlapping clock phases (PH0, PH1) Adjacent stages are also connected via a validation line (IN.sub.-- VALID, OUT.sub.-- VALID) and an acceptance line (IN.sub.-- ACCEPT, OUT.sub.-- ACCEPT), and in some embodiments also via an extension bit line (IN.sub.-- EXTN, OUT.sub.-- EXTN). Input data is transferred from any stage to the following device on every complete period of both clock signals only if both the validation and acceptance signals in the respective latch are in an affirmative state, whereby data is transferred between stages regardless of the state of the validation and acceptance signals in other stages. A two-wire interface is thus formed between the stages.

Abstract: An MPEG decoder operates in 2.5 frame store mode, and has an efficient memory management which allows a B picture to be stored and displayed while simultaneously making use of a portion of the frame store memory. The video frame is treated as a grid, having rows of 8.times.8 pixel blocks. The pixel blocks are manipulated in three FIFOs which are cross-connected in a closed loop. Two processes operate on the memory so arranged: (1) a video reconstruction process which writes data into the memory, and (2) a display process, which accesses the memory and writes the video frame into another, external memory in a rastered format. One of the three cross-coupled FIFOs is designated for write-back, and the other two for reading 2:1 interlaced raster data. The two FIFOs utilized for the raster operation are allocated to the alternate lines of the picture.

Abstract: The present invention includes a method and apparatus for reducing the width of a mark written in optical media. When forming a long mark, the prior art recording methods typically cause blooming at the edges of the mark, resulting in a wide mark pattern which may be sensed by the read focused spot reading an adjacent track causing increased adjacent track crosstalk (ATC). However, by removing every other pulse from the write pulse waveform, the cooling sequence of the writing process is sufficiently increased to allow for additional cooling between pulses. When forming marks with less pulses, the effects of blooming are substantially reduced. Thus, because of the reduction in the effect of blooming, the problems associated with ATC, whereby adjacent track information is recorded, is substantially reduced.