Abstract: A magnetic bubble domain memory device is provided that includes a magnetic domain data chip having a major-minor loop organization with on-chip firmware providing redundancy information enabling the use of the chip even though one or more defective minor loops may be present thereon. One of the pages is written in the minor loop, where a page is defined as a common bit position in each of the plurality of minor loops, with a series of magnetic domains having an odd total number. The next succeeding page in the minor loops contains a series of magnetic domains and voids which are representative of the loop numbers of defective minor loops on the chip with the remaining pages in the minor loops having an even number of magnetic domains contained in each of the pages. Collectively, the pages containing the odd and even number of magnetic domains together with the page containing the map of the defective minor loops comprise the on-chip firmware providing redundancy information.

Abstract: A method and apparatus for synchronizing a digital data demodulator to a received phase modulation carrier signal in which the carrier signal is phase shifted during each modulation period of the carrier to represent one of four pairs of binary bits or dibits. A dibit clock is adjusted to the phase of a reference dibit clock whose output is used to synchronize the demodulator in establishing the location of the modulation period of the incoming carrier. In order to overcome errors found in the decoding of the carrier signal, the adjustment of the dibit clock is suppressed when the dibits 00 and 10 are being decoded.

Abstract: An optical sensing member for reading a coded member having parallel aligned tracks of data and clocking coded symbols which includes a pair of sensing apertures offset to enable the sensing of the data track to occur out of phase with the sensing of the clocking track. The sensing member includes a housing having a sensing surface in which the offset apertures are located, a light source, a pair of photo-transistors for sensing the tracks of coded symbols and optical fibers for transmitting light from the light source to the tracks of coded symbols and the reflected light to the photo-transistors for the reading of the coded members.

Abstract: A symbol decoding system incorporated in a plurality of NMOS/LSI chips generates data representing numerical characters encoded in the symbol. Scanning means generates signals in response to the scanning of a plurality of bars and spaces, which signals are decoded by a first chip as valid and invalid characters, the valid characters being recognized by a second chip which stores the valid characters and enables a microprocessor chip to receive the valid characters assembled as part of the symbol for processing thereof. Logic circuits enable test numerical characters to be generated in response to test signals outputted by the microprocessor chip.

Abstract: A data processing system is disclosed in which a high-speed processor is added to a slow-speed processor and in which both processors have access to a first memory unit with the slow processor having access priority over the fast processor. In order to allow the fast processor to operate without losing data when a conflict occurs during a write operation, a second memory is coupled to the fast processor in which is stored all the data stored in the first memory. When the fast processor attempts to write into both memories but fails to write into the first memory due to a conflict with the slow processor, the data stored in the second memory is then transferred to the first memory subsequent to the completion of the access operation by the slow processor. This arrangement allows the fast processor to complete the write operation interrupted by the conflicts with the slow processor, thereby allowing the fast processor and the slow processor to have access to the same data.

Abstract: A speed control circuit for a motor is responsive to variations in motor supply voltage and torque wherein a digital output indication of the actual speed of the motor is generated. The digital output is converted to an analog value and applied to a comparator which also receives the output voltage of a ramp circuit based on the motor supply voltage. The output of the comparator controls the width of the motor voltage pulses applied from a power amplifier to the motor in which the voltage pulses applied have proportionally larger width for a smaller level of motor supply voltages or decrease in the amount of motor shaft speed and proportionally narrow width pulses for increased levels of motor supply voltage or an increase in the amount of motor shaft speed. A one-shot network is provided for motor stall protection.

Abstract: A method and apparatus for processing data used in a character recognition system in which a threshold voltage value is developed to be applied to an analog waveform representing an unknown character to determine the start of the character waveform. Samples of the first peak of the waveform are generated and a value representing the area under the first peak is developed. Data processing means divides the area by the number of samples taken to arrive at a threshold voltage value which, when applied to the samples taken, determines the start of the character waveform. The voltage amplitudes of adjacent samples of the character waveform are then averaged and the number of samples reduced by one half. A predetermined number of samples having the maximum voltage amplitudes located within peak areas of the waveform are normalized for use by a utilization device in recognizing the unknown character.

Abstract: A character recognition system is disclosed in which feature characteristics of an analog waveform representing an unknown character are applied to a plurality of templates each representing a known character and consisting of a number of windows in which the feature characteristics of the known character are to be located. Hardware implemented circuits compare each feature characteristic of the unknown character with each window of the template. If a feature characteristic is found outside the window, the distance between the location of the feature characteristic from the location of the window is found. The sum of the distances for each template is generated and the templates having the two minimum distances are selected and evaluated to determine if a character can be recognized from the value of the two minimum distances.

Abstract: A data store and retrieval system is disclosed in which a pair of RAM buffer memories are coupled to a CCD page main memory to provide high-speed read/write access by a computer to the main memory. Each buffer memory has stored therein a page of data transferred from the CCD main memory. Compare means included in the system compares the page address requested by the computer with the page address stored in the buffer memories. If a comparison is found, the designated buffer memory is accessed for the requested data. Both read/write access is available under these conditions. If a no comparison is found, logic circuits located in the system using the requested page address transfer the page in which the requested address is located from the CCD main memory to the RAM buffer memories for access by the computer.

Abstract: To effect an accurate transmission of data between processing equipment and a plurality of peripheral devices, first and second interfaces are employed for reconstructing and transmitting the data over a communications link such as a conductor pair. The first interface termed a master terminal which is coupled to a common control module by way of a common control bus, receives instruction, address, and data information from the processor, and transmits a serial data code containing all this information to a plurality of second interfaces, termed slave terminals. Each slave terminal is coupled to a set of peripheral devices by a common bus and when a peripheral device recognizes its address being present in the code received from the master terminal, the slave terminal responds to complete the transaction with the master terminal and the addressed peripheral device.

Abstract: A transition code processing system which includes a record member on which is located a plurality of bar code symbols, each of which comprises a data channel and a clocking channel. The record member is inserted into a data terminal device and intermittently driven through a printing station in which a sensing member senses the data channel out of phase with the sensing of the clocking channel and generates signals in response thereto. A circuit coupled to the sensing member will process the generated signals and transmit the processed signals to a utilization device. Upon processing the signals representing the last bar code symbol on the record member, the circuit will generate a control signal for stopping the movement of the record member through the printing station, thereby conditioning the record member for a subsequent printing operation.

Abstract: A symbol decoding system incorporated in a NMOS/LSI chip generates asynchronously binary data in response to the scanning of bars and spaces of the symbol. The binary data may represent each bar or space as a numerical character, a margin or a center band of the symbol. The binary data also includes data identifying the bar or space and if the character generated is valid or invalid. Logic circuits generate a time delay period allowing the binary data to be generated asynchronously during the delay period. At the end of the delay period the binary data is outputted to a utilizing device for selecting the valid data from the data outputted by the decoding system.

Abstract: A method and apparatus for controlling the refreshing of a volatile memory is disclosed in which conflicts between a memory refresh operation, the requirements for access to the memory during a data processing operation and a power up or power down condition are resolved. When a conflict occurs, clock signals are generated to provide a contention refresh operation of the memory with minimum interruption to normal access time between the control processor and the memory.

Abstract: A driving circuit arrangement for a gas-discharge display device operated asynchronously by a blanking signal generated in a processor applies a voltage level to each of the cells of the display device which is below the voltage level required to fire the cells upon the generation of the blanking signal. This arrangement enables the selected cells to fire upon the subsequent removal of the blanking signal. Switching members are operated by the generation of the blanking signal to precharge each of the cells in the display device during the blanking interval in which data transmitted from the processor selects the character to be displayed.

Abstract: A control circuit limits the power supplied to a bar code reader system only to the particular point in time that a bar code located on a record member is being read by an optical wand. Control signals are generated during the time the reader system is not in a reading mode, which reduces the amount of power supplied to the reader system. Upon entering a read mode as determined by signals generated by the optical wand, power is supplied for a predetermined time sufficient to read the bar code on the record member. A plurality of single-shot multivibrators generate control signals for cyclically interrupting the power supply when the reader system is in a non-read mode, thereby reducing the amount of power consumed by the reader system.

Abstract: A system and apparatus for compressing a binary data message generated by a digital input device is disclosed wherein a data message generated in a data terminal device as part of a merchandise transaction is examined on the basis of information content with all data relating to redundant information previously generated or known being deleted together with encoding of preselected portions of the non-redundant data results in the compression of the data to a minimum amount without losing the informational content of the original data thereby allowing the compressed data to be stored in a relatively small storage unit located in the data terminal device. A compressed data record is generated including an encoded start of record character which may signify, in addition to the start of the compressed data record, the type of merchandise transaction being processed.

Abstract: A light pen detection system used in a data display system utilizes a cathode ray tube (CRT) in which characters displayed on the screen of the cathode ray tube are detected by the light pen, the detection of the character by the light pen resulting in the background inversion of the character sensed thereby providing a visual indication to the operator the character sensed by the light pen. A locking circuit is provided which, upon the sensing of a displayed character by the light pen, conditions the sensing circuits connected to the light pen to continually output the character sensed until the light pen is moved completely away from the locked character.

Abstract: A holographic scanning system for scanning a bar code indicia is disclosed in which the light beam of a laser is split into two segments, each directed through a plurality of holograms mounted on a single rotating disk for generating a scanning pattern comprising a plurality of intersecting lines on a target area through which passes a label or object bearing a bar code indicia. The light reflected from the bar code indicia is picked up by an optical detector for use in reading the bar code. A second embodiment includes a rotating disk having mounted thereon two holograms each offset to the other which generates a semicircular scan pattern used in generating an X scan pattern on the target area.

Abstract: A distributed multiprocessor communication system, wherein the central processing unit (CPU) is relieved of the burden of bus management by a scheme which multiplexes the interprocessor module communications bus, to which all processors are guaranteed access, so that only an addressed CPU may be interrupted from performing its dedicated data processing function. Associated with each independent processor is a communications interface unit or communications network routing unit which relieves the processor of the task of decoding communications on the interprocessor or intermodule communications bus and, in addition, upon decoding its address and buffering message data, transmits a "handshake" signal over the bus back to the sender during a designated time slot, thereby informing the sender that the transmitted message was actually received.