Abstract: In a data processing system, a circuit for providing an even bus clock signal, EVENBCLK, when the leading edges of the bus clock signal BCLK and a processor clock signal PCLK are coincident includes a phase-locked loop unit and a coincidence unit. The phase-locked loop unit provides PCLK signals that have a frequency Nx the frequency of the BCLK signals, where N can have an integer or a half integer value. The phase-locked loop unit includes a divide-by-M unit, where M=2N, that receives the PCLK signal at an input terminal and applies an output signal, PCLK/M, to the phase detector unit of the phase-locked loop unit. The operation of the phase-locked loop results in the BCLK signal and the PCLK/M signal having an established phase relationship. The PCLK signal and the PCLK/M signal are applied to the coincidence unit, the simultaneous application of the two signals resulting in the coincidence unit providing the EVENBCLK signals.