Abstract: Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.

Abstract: A differential current-sensing amplifier includes two inverters, two resistors, a NOR gate, and five switches. The first inverter has a first output; the second inverter has a second output. The first resistor is connected between the first inverter and ground; the second resistor is connected between the second inverter and ground. A current to be sensed is input between the first resistor and the first inverter; a reference current is input between the second resistor and the second inverter. The first switch is connected between the first output and ground, the second switch is connected between the second output and ground, and the third switch is connected between the first and the second inverters and power. The first and the second switches are turned off, and the third switch is turned on, to compare the current to be sensed in relation to the reference current.