Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an IC design which tests a set of dummy devices that are identical to a selected set of devices contained in the IC. The device test structures are selected from a library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured.

Abstract: A phase metrology pattern for attenuating phase masks. The phase error of this pattern can be determined to high accuracy by aerial image measurements. This pattern can be used to create an optical phase standard for calibrating phase metrology equipment for attenuated phase masks, or as a witness pattern on a product mask to verify the phase accuracy of that mask. The pattern includes an effective line to space ratio and can be tested using a microscope or stepper system or can be measured directly using a detector for the 0 order diffraction measurement.

Abstract: A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.

Abstract: The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

Abstract: Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.

Abstract: A method and apparatus that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.

Abstract: A method and apparatus for transmitting data packets in an integrated circuit according to a data integrity scheme that embeds an integrity value in each data packet. As the data packets are transferred, the data integrity value for a data packet is stored during a stall of the transmission of that data packet so that the stored integrity value can be used after the stall has ceased.

Abstract: A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting a element across the respective source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. The method includes connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: Asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl).

Abstract: A memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access command signal (ACMDS) enabling commencement of memory access, and a command discriminating circuit (CMDDEC) that receives the first (CE) and second (ADV) input signals, a third (OE) and a fourth (WE) input signals, and a clock signal (CLK), and that outputs a command discriminating signal (WRITE) for specifying whether the access command signal is for a read operation or a write operation.

Abstract: The objective of the present invention is to provide a semiconductor storage device wherein a low active current is obtained by reducing the number of sense amplifiers to be activated at a time. An SDRAM has a divided word line structure, and includes a plurality of banks, each of which includes arrays AR1 to AR64 and 4K main word lines MWL. A row address signal is fetched in response to a row address strobe signal, and a segment address signal is fetched in response to a column address strobe signal. A main row decoder MRD activates main word lines MWL1, MWL5, MWL9 and MWL13 in response to the row address signal, and a segment row decoder SRD selects only an array AR1 in response to a segment address signal, and activates only 1K sense amplifiers SA corresponding to the selected array AR. When the main word lines MWL1, MWL5, MWL9 and MWL13 are activated, the segment word lines in arrays AR2 to AR64 are not activated, so that data are not destroyed.

Abstract: A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house.

Abstract: A body-biased enhanced current mirror circuit is disclosed wherein the body voltage of a current mirror device is adjusted to compensate for the effect of changes in the output voltage on the output current, increasing the output impedance. For each instance of the current mirror, this approach has the advantage of requiring no additional margin in operating voltage and of consuming no more circuit area than prior art current mirror designs. In addition, the body-biased enhanced current mirror circuit provides a stable reference current to output current ratio over a wide operating range. An auxiliary MOSFET current mirror device with the body connected to ground may be added in parallel with the body-biased current mirror device to eliminate a non-monotonicity of the current output.

Abstract: A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

Abstract: An asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.

Abstract: A differential current-sensing amplifier includes two inverters, two resistors, a NOR gate, and five switches. The first inverter has a first output; the second inverter has a second output. The first resistor is connected between the first inverter and ground; the second resistor is connected between the second inverter and ground. A current to be sensed is input between the first resistor and the first inverter; a reference current is input between the second resistor and the second inverter. The first switch is connected between the first output and ground, the second switch is connected between the second output and ground, and the third switch is connected between the first and the second inverters and power. The first and the second switches are turned off, and the third switch is turned on, to compare the current to be sensed in relation to the reference current.

Abstract: Disclosed is a circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting an element across the source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.

Abstract: The objective of the present invention is to provide a DRAM that reduces the current consumed by an address comparison circuit that compares an address signal with a defective address signal that has been programmed. Redundant predecoders predecode a defective row address signal DRA output by program circuits, and an address comparison circuit compares a predecoded signal, output by a predecoder, with the defective predecoded signals PDRA, output by the redundant predecoders. In the case of a 2-bit predecoding system, the address comparison circuit compares the predecoded signal PRA with the defective predecoded signal PDRA using four bits in order to compare the row address signal RA with the defective row address signal DRA using groups of two bits.

Abstract: An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.