Abstract: In some embodiments a connector is to couple a peripheral, and a detector coupled to the connector is to detect if the peripheral is disconnected from the connector in response to a first reserved pin and a second reserved pin.

Abstract: A mechanism is provided at a host system to allow multiple entities (clients) to send and receive messages of a particular class of management services in a switched fabric for scalable solutions.

Abstract: A host system is provided with a shared resource (such as work queues and completion queues); multiple processors arranged to access the shared resource; and an operating system arranged to allow multiple processors to perform work on the shared resource concurrently while supporting updates of the shared resource. Such an operating system may comprise a synchronization algorithm for synchronizing multiple threads of operation with a single thread so as to achieve mutual exclusion between multiple threads performing work on the shared resource and a single thread updating or changing the state of the shared resource without requiring serialization of all threads.

Abstract: In some embodiments, a memory transaction is received that was sent over an unordered interconnect. A determination is made as to whether an address conflict exists between the memory transaction and another memory transaction. If the address conflict exists the memory transaction is forwarded only after waiting until the conflict is resolved. Other embodiments are described and claimed.

Abstract: In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.

Abstract: In some embodiments, a first comparator compares a first error rate and a first threshold value and a second comparator compares a second error rate and a second threshold value. Other embodiments are described and claimed.

Abstract: A method and system for accessing devices through use of an abstraction layer interface that “hides” the access methods from components accessing the devices, such as device drivers and OPROMs. The abstraction layer interface includes a set of resource access methods and a database containing bus, device, function and resource information for various devices in a system. During an initialization process, bus and device configuration information is determined and stored in the database. When an application or operating system requests access to a device, the application or OS uses the device's device driver or OPROM to pass identification information, resource information and one or more resource access commands to the abstraction layer interface, which then verifies the identification information against the database, and converts the resource access request into appropriate resource access methods that are used to access the device.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine (ME) arranged to establish connections and support data transfers, via a switched fabric, in response to work requests from a host system for data transfers; interface blocks arranged to interface the switched fabric and the host system, and send/receive work requests and/or data messages for data transfers, via the switched fabric, and configured to provide context information needed for said Micro-Engine (ME) to process work requests for data transfers, via the switched fabric, wherein the Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks in parallel in order to process data messages.

Abstract: A port configuration mechanism is provided at a host for multiple port allocation and shared resource utilization to support multiple port configurations for different port operation modes on a host to handle data transfers in a switched fabric data network for scalable solutions.

Abstract: A circuit includes an operation unit adapted to perform a circuit operation in a plurality of rounds. The operation unit may operate properly under a predetermined range of operating conditions. The operation unit is adapted to select between receiving an input signal and a test signal and to perform a test round of the circuit operation when the test signal is selected. The circuit is adapted to compare a reference value with a result of the test round, the reference value identifying a correct value for the result of the test round when the operation unit is operating under the predetermined range of operating conditions. The operation unit is further adapted to receive a disable signal to disable the operation unit from performing the circuit operation when the result of the test round does not match the reference value. Other embodiments are described and claimed.

Abstract: A method and apparatus for enabling hardware platform identification while ensuring privacy protection. The apparatus comprises a computer-readable medium that stores computer-executable instructions. Those instructions, when executed by a microprocessor, cause an expected hash value, which is derived from a key and a first identifier for a computer system; to be compared with a hash value, which is derived from the key and a second identifier for a computer system. A microprocessor for executing those instructions may comprise an identifier that identifies the microprocessor, and embedded instructions for comparing a hash value, derived from the identifier and a key, to an expected hash value.

Abstract: A dynamic workload feedback mechanism is provided at a service provider to notify a client a current workload of the service provider in a switched fabric in order to prevent unnecessary timeouts and retries of duplicate service requests.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine arranged to establish connections and support data transfer operations, via a switched fabric, in response to work requests that cause instructions in a form of work queue elements “WQES” posted from a host system for said data transfer operations; and a work queue element “WQE” hardware assist “HWA” mechanism arranged to determine the starting address of each work queue element “WQE” based on queue pair (QP) context information needed for said Micro-Engine (ME) to process work requests for said data transfer operations.

Abstract: For one embodiment of the present invention, a processor may include one or more integrated voltage regulators powered by an external voltage regulator and generating one or more local supply voltages for the processor. The one or more local supply voltages may be set to allow one or more circuits powered by the local supply voltage(s) to meet a timing requirement. The local supply voltage(s) may be adjusted by the processor in accordance with a power management policy.

Abstract: According to one embodiment, a printed circuit board (PCB) is disclosed. The PCB includes a first functional unit block (FUB) and differential traces coupled to the first FUB. The first FUB transmits high-speed serial data. The differential traces carry the high-speed serial data from the first FUB. In addition, the differential traces crossover on the same layer of the PCB while maintaining a constant impedance.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine (ME) arranged to establish connections and support data transfer operations via a switched fabric; a serial interface arranged to receive and transmit data packets from the switched fabric for data transfer operations; a host interface arranged to receive and transmit host data transfer work requests from the host system for data transfer operations; a context memory arranged to provide context information necessary for data transfer operations; a doorbell manager arranged to update the context information needed for the Micro-Engine (ME) to process host data transfer requests for data transfer operations; and, a remote key manager arranged to manage remote keys and check the validity of the remote keys which correspond to outstanding data transfer operations.

Abstract: A computer system having multiple components capable of being in either a wake or sleep state includes a power manager and a voltage regulator. The power manager may generate a power state status signal indicating the power states of the components, and this signal may be provided to the voltage regulator. In response, the voltage regulator may operate in a synchronous mode when the power state status signal indicates that the components are in a wake state. The voltage regulator may operate in a non-synchronous mode when the power state status signal indicates that the components are in a sleep state.

Abstract: Multiple (e.g., dual) pass cache defining arrangements for maximizing cacheable memory space.

Abstract: A platform featuring memory which contains a plurality of software components and a manifest which includes a digest of each of the plurality of the software components and a processor which is coupled to the memory. The processor executes a hash function to produce the manifest and to verify integrity of the plurality of software components by re-computing digests of the plurality of software components and comparing the computed digests with the digests of the manifest.

Abstract: Cache defining arrangements for maximizing cacheable memory space, including a mixed technique scheme using a bottom-up scheme defining a first non-memory-hole portion using mainly substantially additive blocks of cacheable space, and a top-down scheme defining a second non-memory-hole portion by defining an oversized block of cacheable space and using mainly substantially subtractive blocks of cacheable space.