Abstract: A fuse for a semiconductor integrated circuit is provided wherein a strip of corrosive material (82), such as aluminum, has one end thereof connected to a conductive strip (84) of a non-corrosive material and the other end thereof connected to a strip (94) of non-corrosive conductive material. The one end of the conductive strip (82) connected to the conductive strip (84) is connected through a contact (88). Similarly, the other end of the strip (82) is connected through a contact (96) to the non-corrosive conductive strip (94). The strips 84 and 94 provide a barrier to corrosion. This occurs whenever a break (104) is formed in the fuse to expose the ends of the fuse (82) at the break to a corrosive atmosphere. Alternatively, the fuse could be connected to corrosive underlying layers with contacts (118) and (124) of non-corrosive material such as a polysilicon or a polyside, or the active region of the substrate itself.

Abstract: A method of forming a planar dielectric layer over an interconnect pattern which requires fewer processing steps and has a lower dielectric constant than is obtained in the prior art. The method comprises providing a substrate having an electrical interconnect pattern thereon, forming a first layer of dielectric over the interconnect pattern, preferably by plasma generated TEOS oxide, forming a porous second layer of silicon-containing dielectric with low dielectric constant different from the first layer over the first dielectric layer from an inorganic silicon-containing composition, preferably hydrogen silsesquioxane and forming a third layer of dielectric different from the second layer over the second dielectric layer, preferably by a plasma generated TEOS oxide.

Abstract: A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.

Abstract: A redundancy passgate circuit is implemented in NMOS technology in order to provide a more rapid transmission of the transmitted signals. The circuit provides for the more rapid signal transmission by reducing the capacitance experienced by the input signals. The reduced capacitance loading is achieved at the expense of a greater layout area and a requirement for an on-chip power supply.

Abstract: A remote control access system uses a transmitter and a receiver. The transmitter generates an encrypted identification code which the receiver decrypts and grants access to the system if the decrypted code matches an identification code stored in the receiver. The encryption occurs by taking a 40 bit identification code and forming 5 bytes (8 bytes each). The 5 bytes are logic exclusive OR'd to form a 5 byte wide encrypted code. Decryption occurs by performing the opposite exclusive OR operation on the 5 byte wide encrypted code to convert it back to the 5 byte identification code. The 4 most significant bytes of the decrypted code are compared against the 4 most significant bytes of the previous stored decrypted code in the receiver. If the comparison yields a zero, this means the least significant byte will be within 2.sup.8 or 256 of each other and access will be granted.

Abstract: The invention is a single piece deep downset exposed lead frame (10) that can be used in current production processes. A single lead frame (10) has a die mount pad (12) that is formed with a downset or cavity into which the semiconductor die (20) is mounted. Wings (14, 15, 17, 18) lock the die pad in the device package (21) and increase the length of potential moisture paths (34a). The downset die pad (12) provides direct thermal contact of the die mount pad (12) to an external heat sink, eliminating the need for a heat slug internal to the package. The exposed die pad (12) can also be used as an RF ground connection to an RF circuit ground plane.

Abstract: A hybrid leadframe-over-chip (LOC) semiconductor package is generally comprised of bonding finger elements located over a surface of a semiconductor component and electrically coupled, by means of conducting wires, to the bonding pads located on the surface. In addition, at least one bonding finger is located outside the boundary of the surface of the semiconductor component. Each bonding finger located outside the boundary is coupled, by a conducting wire, to a bonding pad positioned within the boundary of the semiconductor component. In this manner, for a given semiconductor component size and for given routing and lead dimension constraints, a larger number of conducting paths can be provided between the leadframe and the semiconductor component.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: An improved electrically erasable read only memory (EEPROM) includes a EEPROM cell and a static random access memory (SRAM) cell. Complementary pairs of complementary metal oxide semiconductor (CMOS) transistors connect the gates of transistors forming the EEPROM cell to either the corresponding data nodes of the SRAM cell or to a fixed read or nonzero test voltage. When formed into an array, it is not necessary to replicate differential sense circuitry in every cell. EEPROM transistor pairs are combined into columns which share a common sense latch. The nonsero test voltage allows for measurement of the actual threshold voltages (V.sub.T) of each EEPROM device individually.

Abstract: An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.

Abstract: An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.