Abstract: An adder provides either binary or binary coded decimal operation under the selection of a control input. The data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits. Outputs, in addition to the four bit result, include carry propagate and carry generate signals for the four bit group. Binary operation is conventional. For binary coded decimal operation, the adder corrects an initial binary result to the binary coded decimal format by adding six when there is a group carry generate signal present thus forming an intermediate result. This intermediate result is formed before the occurrence of the carry in from a preceding stage. In the final stage of the adder, the intermediate result is incremented to form the final four bit result if there is a carry in.

Abstract: A family of operational amplifiers are described which utilize only MOSFET transistors as the active devices. These operational amplifiers exhibit an infinite input impedance and zero input offset and bias currents. The circuits are capable of operating over a wide range of DC supply voltages at extremely low DC current drain. An operational amplifier is shown which operates from a single positive DC supply voltage and which handles a wide range of input common mode voltage swings including some negative common mode voltages. Another operational amplifier is shown which operates from a combination of a single positive and a single negative supply voltage and which handles a wide range of positive and negative input common mode voltage swings.

Abstract: An integrated circuit structure is provided in which component isolation is achieved after all diffused junction formation is complete. An anisotropically etched moat provides isolation. The surfaces of the moat are lined with oxide and a planar wafer surface is restored by filling the moat with metal. The subsurface metal region can then be used as a conductor for component interconnection.

Abstract: A double master mask process for fabricating semiconductor integrated circuits is provided in which selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits with a minimum number of critical alignments. A first silicon dioxide silicon nitride layer used in conjunction with a first master photomask defines a base region and an isolation region which are self-aligned with respect to each other and with respect to resistor contact regions. After isolation and base diffusion, the first oxide/nitride layer is stripped away and a second oxide/nitride layer is grown. Using a photoresist mask, a predeposition layer for the resistor is then formed using ion implantation through the oxide/nitride layers. A second master photomask allows the formation of collector and emitter regions and base and resistor contact which are self-aligned with respect to each other.

Abstract: A high heat dissipating integrated circuit device having a large heat sink metalic portion surrounding the plastic encapsulation material of the semiconductor chip. The semiconductor chip is mounted in electrically insulated, close conjunction with the heat sink such that high heat dissipation is provided. The heat sink portion is conveniently formed surrounding most of the plastic encapsulation to provide for maximum heat dissipation from the device. The device provides for heat dissipation in the ten to higher watt range.

Abstract: An improved lead frame is provided for the manufacture of high heat dissipating semiconductor devices having a large heat sink metallic portion exposed with plastic encapsulating material partially disposed thereabout. A semiconductor unit is mounted directly on the heat sink such that high heat dissipation is obtained. The lead frame provides for pairs of metallic heat sink portions joined to a interdigitated center lead frame portion such that the interdigitation of the semiconductor device leads associated with each of the opposed heat sink portions provides for a high density lead frame structure from which a minimum of material must be removed in the fabrication process.

Abstract: A bidirectional line driver circuit for transmitting logic signals on a highly capacitive, or low impedance transmission line makes use of a tandem connection of switching means for providing a low impedance connection from the output of the driver circuit to either a first power supply voltage or a second power supply voltage to define transmitted logic levels. Coupled to the tandem switching means is a buffered feedback circuit which responds to conduction of the first switching means connected to the first power supply voltage such that nonconduction is produced in the second switching means connected to the second power supply voltage. A buffer transistor is incorporated in the feedback circuit to insure that this response occurs without significant loading of the output terminal thus eliminating the possibility of oscillation and providing for very high speed switching performance.

Abstract: A method for removing slag and debris from the surfaces of laser scribed semiconductor die is provided in which the die and glass or metal beads are placed into a cylindrical wire mesh basket and the basket is turned causing the beads and die to mechanically mix. The mechanical mixing action removes debris and slag which subsequently falls through the wire mesh of the basket so that the die surfaces are not marred.

Abstract: An improved method of semiconductor device manufacture is provided in which the surfaces of glass sealed feed-through terminals are mechanically abraded to a uniform matte finish prior to plating and subsequent assembly. The mechanical abrasion, which in the preferred embodiment is performed by dry sand blasting, reduces the cost and improves the yield in subsequent assembly bonding steps and in particular substantially eliminates cold forming defects on the terminal nail head surface such that electrical conductors can be ultrasonically bonded thereto.

Abstract: A logic circuit uses an input Schottky diode of a first threshold and a clamp Schottky diode of a second threshold in combination with a high speed NPN switching transistor to form a simple high speed logic element. The novel use of two Schottky diodes of different threshold voltages provides a logic gate with a lower logic swing amenable with higher speed operation. Further, the operation of the logic gate is independent of the temperature characteristics of the NPN switching transistor. A PNP current source provides the drive current and load current for the logic gate in a simple manner which uses minimum chip area.

Abstract: A method of surface treating aluminum, particularly aluminum metallization for semiconductors, which includes subjecting the aluminum surface to be treated with fuming nitric acid for one to ten minutes at room temperature. Following cleaning, the surface is subjected to boiling water for 5 to 15 minutes. The foregoing treatment appears to form a boehmite (AlO(OH)) layer on the surface of the aluminum, thereby substantially eliminating hillocking.