Abstract: Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

Abstract: Methods and apparatus for loading a security algorithm in a fast path of a network processor are disclosed. In an example method, a network processor generates a statistic associated with a plurality of communication packets received by the network processor, determines a security attack on the network processor is in progress based on the statistic and loads the security algorithm in the fast path of the network processor.

Abstract: In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

Abstract: In general, in one aspect, the disclosure describes a method that includes accessing a packet, determining a flow associated with the packet, and determining, based at least in part on the packet, whether to remove the flow from a list of flows to handle using page-flipping.

Abstract: In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.

Abstract: In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

Abstract: A method, apparatus, and signal-bearing medium for indicating and responding to congestion in a network. When a buffer at a receiver is nearly full, the receiver may send a congestion indication to the sender(s) that is causing the congestion. When the receiver(s) receives the congestion indication, it may implement a flow-control technique to temporarily lower the rate that it is sending the frames to the receiver, and then increase the rate.

Abstract: A method of maintaining network protocol timers in data structures associated with different respective processors in a multi-processor system. The timers accessed by a respective one of the processors include timers of connections mapped to the processor.

Abstract: The present disclosure describes a method comprising issuing a plurality of commands to a controller, wherein the commands are issued in a first order, and wherein the completion status of commands is written to the memory in a second order, and wherein the second order may be different from the first order. Also described is an apparatus comprising a controller adapted to accept a plurality of commands, wherein the commands are issued in a first order, and completion status of commands is written to the memory in a second order, and wherein the second order may be different from the first order.

Abstract: In general, in one aspect, the disclosure describes a method of determining a checksum. The method includes accessing a checksum of the at least the portion of a packet and adjusting the checksum based on a subset of the at least the portion of the packet before and after modification of the subset.

Abstract: In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random Access Memory (RAM) and selecting one of the commands based, at least in part, on the memory access operations identified by the commands and the memory access operation of a previously selected memory access commands.

Abstract: A system and method of transmitting network packets between network processing elements through links are disclosed. One or more configuration entities may allocate one or more fixed length slots to be appended to network packets forwarded on a link between network processing elements in-band of the link.

Abstract: A module to perform system management for a computer. The module includes a memory to store management event information and a controller to operate in an active central management controller mode and in a standby central management controller mode. In both modes the controller sends system event information to another controller to duplicate the management event information.

Abstract: In general, in one aspect, a method is provided for of tracking a network statistic stored within a collection of bits. The method includes storing the collection of bits storing the network statistic as at least a first portion and a second portion. The first portion includes a set of least-significant bits and the second portion includes a set of more significant bits. The method also includes incrementing the first portion based on a packet and determining if the incrementing of the first portion caused a designated bit of the first portion to be set. If it is determined that the incrementing of the first portion caused the designated bit to be set, the method increments the value stored by the second portion and resets the designated bit within the first portion.

Abstract: The present application describes a compiler of a network packet classification programming language that generates code for processors such as an application processor and a processing engine. The programming language includes a variety of instructions including an instruction to declare a network protocol and an instruction to specify a rule and at least one action to perform if the rule applies. A processor executing instructions generated by the compiler assigns values based on instructions to declare a network protocol and applies the rule instructions to received packets. The programming language may also include other instructions such as an instruction to search a set of values and identify whether an encapsulated packet header is present in a packet.

Abstract: In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

Abstract: The disclosure includes a description of a content addressable memory (CAM) that includes at least one tag input and at least one random access memory. The CAM also includes circuitry to perform multiple read operations of the at least one random access memory with multiple, different ones of the read operations specifying an address based on different subsets of tag bits. The circuitry includes digital logic circuitry coupled to the at least one random access memory to determine whether a lookup tag matches a subset of the different subsets of tag bits.

Abstract: Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.

Abstract: The disclosure includes description of a method of processing packets using threads. The method includes processing a packet by a single thread in a first packet processing pipeline stage and processing the packet by multiple threads in a second packet processing pipeline stage.

Abstract: Described herein are techniques to perform reassembly of a Transmission Control Protocol (TCP) data stream from payloads of TCP segments of a bidirectional TCP connection between a first TCP end-point operating at a first network device and a second TCP end-point operating at a second network device.