Patents Represented by Attorney, Agent or Law Firm Robert A. Skrivanek
  • Test circuit for memory
    Patent number: 6611929
    Abstract: A test circuit for memory having plural memory cells and address latches responsive to addressing circuitry for reading/writing to said memory cells in a normal mode, has first connecting circuitry for connecting the address latches to form a linear feedback shift register. The linear feedback shift register is responsive to a clock signal to provide a sequence of addresses for testing the memory in a test mode.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: August 26, 2003
    Assignee: STMicroelectronics Limited
    Inventor: William Barnes