Abstract: A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.

Abstract: A structure and method for identifying a physical location of a defect in a logic circuit based on a physical location of a logic latch having failing data. The logic circuit includes a plurality of logic latches, each having a predetermined physical location within the logic circuit. The logic latches are connected to devices adjacent the logic latches, such that the failing data in the logic latch indicates a failure of a device adjacent the logic latches.

Abstract: A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.

Abstract: A system for modifying the power up and diagnostic procedure of systems such that the system voltage is lowered to a predetermined voltage level that has been shown to detect delay faults. The system conducts the normal procedure of power up/diagnostic routines at the described VLV condition and then logs failures to this VLV condition. Upon completion of the VLV power up, the system is shut down normally and then subsequently powered up again at the normal voltage conditions. Discrepancies between the VLV power up/diagnostics are noted in the system log and communicated appropriately.

Abstract: A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macro's are inverted with respect to adjacent macros to balance parasitic capacitances across the array.

Abstract: A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.

Abstract: A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used.

Abstract: A structure for testing external connections to semiconductor devices. The structure includes an external electrical path between selected external connections on the semiconductor devices.

Abstract: A method and system for testing wafers, and particularly a wafer test system employing probes to provide for electrical contact with a device under test (DUT) which is located on a wafer. More particularly, also provided is a method and system for implementing wafer tests where the probes first contact a simulated wafer which incorporates an array of spaced load cells to determine the optimum probe overdrive. The DUT is then tested at the optimum overdrive.

Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

Abstract: A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Abstract: A localized direct sense architecture circuit includes a large number (e.g. 8) of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for increased layout density.

Abstract: An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.

Abstract: A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.

Abstract: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

Abstract: A device and method for providing precision alignment and support for an optical film measurement probe in the wafer rinse tank of a CMP polish tool. The device includes of a probe carrier, and spring loaded support guides attached to a support ring that supports and locates the mechanism in the rinse tank of the CMP tool. The probe carrier has multiple beveled bearing pads (three or more) that contact the rim of the rotating wafer chuck. Pressure from the chuck against these pads forces the probe carrier to maintain a fixed distance and orientation relative to the wafer while allowing the smooth rotation and motion of the wafer and chuck. Further, an integrated the wafer spray nozzles can be attached to the probe carrier that is located so as to minimize interference between wafer spraying and the probe carrier.

Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

Abstract: A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area.

Abstract: Disclosed is a programmable impedance driver that includes two sets of impedance devices, two primary counters and two test counters. The primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver and the test counters verify the counting operation of the primary counters during manufacturing testing of the driver. Therefore, the built-in self-test (BIST) aspect of the invention easily detects if one of the counters will become stuck during normal usage.

Abstract: A dynamic random access memory includes first and second address generators, subarrays, an address decode path and a precharge activation path, wherein the precharge activation path and the address decode path are matched. The first address generator identifies a word and a column address. The second address generator identifies a subarray address. The subarrays include a number of cells for storing data. The address decode is configured to transmit address and other information while the precharge activation path is configured to transmit a precharge activation signal. In a preferred embodiment, an event during an active phase process, such as a sense amplifier set signal initiation, initiates the precharge phase process.