Abstract: A differential capacitor structure (10) formed overlying a substrate (12) having a middle layer (24) disposed between a lower layer (18) and an upper layer (28). The lower layer (18) is a static layer that is formed on the substrate (12), the middle layer (24) has a moveable component and is a dynamic layer attached to the substrate (12) using semi-circular tether supports (42), and the upper layer is a static layer that is anchored to the substrate (12). The semi-circular tether supports (42) are formed from a homogeneous material and provide structural stiffness to support the middle layer (24) in space and also provide stress relief.

Abstract: A system (200) comprises a regulator (250), a battery unit (220), a voltage sensitive circuit (210, e.g., memory circuit) and a switchable sensor (280). The battery unit (220), the memory circuit (210) and the switchable sensor (280) are parallel coupled to terminals (266 and 264) of the regulator (250). The switchable sensor (280) itself has a serially coupled voltage sensor (230) and switch (240). In a first operating mode, the regulator (250) provides a voltage V.sub.2 to the memory circuit (210) and to the switchable sensor (280). The switch (240) is closed. The voltage sensor (230) measures the voltage V.sub.2 and communicates the result to the regulator (250) via a signal input (267). In a second operating mode, the regulator (250) does not provide the voltage V.sub.2. The switch (240) is open. The battery unit (220) provides a voltage V.sub.4 to the memory circuit (210), but not to the voltage sensor (230).

Abstract: A multiple-clock-cycle subranging type A/D converter utilizing sufficient fine steps in the LSB identification to cover two complete coarse steps so that there are no gaps in the fine steps and no potential errors. Also, two LSB encoders can be utilized, one during each clock cycle, to increase the speed of the A/D converter. The components of the A/D converter are positioned on a semiconductor chip so that noise from electronic switches is not introduced into the reference voltage ladder.

Abstract: An ECL to TTL translator converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic translations. The ECL input signal is transformed into first and second differentially related currents which develop first and second voltages for biasing first and second switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage includes an upper and lower transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.

Abstract: An analog-to-digital converter is provided wherein an analog input signal and one of a series of predetermined reference potentials are stored across first and second capacitors, respectively, to establish a balanced zero differential signal across the first and second inputs of a comparator. The output signal of the comparator drives a logic circuit for generating first and second portions of a digital control signal wherein the first portion selects between the lower resolution reference potentials searching for a first reference potential of the greatest value which when compared to voltage stored across the first capacitor provides the least magnitude differential signal across the first and second inputs of the comparator thereby resolving a major portion of the analog input signal.