Abstract: An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches.

Abstract: A substantially in situ trench isolation process is provided. The process includes forming a trench regions between active regions in a semiconductor substrate. The semiconductor substrate may be covered with a protective oxide pad and/or nitride layer. In a single chamber, an oxide is thermally grown in the trench, the nitride layer is substantially stripped, and a fill dielectric is deposited in the trench and over the active and trench regions. The invention contemplates thermal growth, etch, and deposition processes to be performed serially in a single chamber without opening the chamber. The invention further contemplates modifying or adapting a conventional process chamber to all for the in situ processing of thermal growth, etch, and deposition processes. Alternatively, a specialized chamber may be provided.

Abstract: An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.

Abstract: An automated system is presented for containerless transfer of semiconductor wafers through a wall separating a first fabrication area and a second fabrication area. The system includes multiple containers for transporting the wafers, one or more air lock chambers, mass transfer systems, robotic arms, stock areas, and a control system. The containers (e.g., wafer boats) are dispersed between the first and second fabrication areas. A portion of the containers contain at least one semiconductor wafer, and the remainder of the containers are empty. The air lock chambers are positioned in sealed openings in the wall. The air lock chambers provide isolation between the first and second fabrication areas while permitting the transfer of semiconductor wafers between the fabrication areas. A mass transfer system is positioned within each air lock chamber and allows for containerless transfer of wafers through the air lock chamber. The stock areas provide storage areas for containers adjacent to each air lock chamber.

Abstract: A system and method for calculating the performance of a cluster tool using a weighted configuration matrix. The system includes a computer system which maintains a database of entities corresponding to semiconductor wafer processing modules in a fab. A user "clusters" the entities, i.e., selects entities to reflect the relationship of the constituent modules physically linked together which form the cluster tool. The user also designates a main module against which the main performance events of the cluster tool, such as begin run and end run, are logged in the database. The computer system configures all of the "up" and "down" state configuration combinations of the cluster tool modules and displays the configurations for the user. The user specifies a weight for each of the configurations based upon an estimate of the performance the cluster tool while in the respective configuration relative to the performance of the cluster tool in a fully operable configuration.

Abstract: A computer-implemented method for aiding in the design of an integrated circuit (IC) floorplan. The method comprises receiving a netlist, physical layout information, and timing constraints of the IC and performing timing analysis of the signal paths of the IC. The user selects the set of nets to by analyzed. The timing analysis comprises calculating net delays as a function of the length of the signal paths. The timing analysis further comprises calculating slack times by subtracting from the clock cycle time of the IC the sum of the driven at timing constraint, the needed by timing constraint, and the net delay. Paths which have a slack time greater than a slack failure value are passing nets and paths which have a slack time greater than a slack failure value are failing nets. The slack failure value is user-specifiable and defaults to zero.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.

Abstract: An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches.

Abstract: An in situ process is provided for isolating semiconductor devices according to a LOCOS process. The invention contemplates performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth all within a single chamber without removing the wafers from the chamber during processing. The invention is believed to result in increased yields and process throughput by reducing the exposure of the wafers to outer-chamber contaminants, thermal stress, and transportation damage, as well as reducing inter-chamber transportation time. The invention also contemplates an in situ processing chamber adapted for performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth as part of a LOCOS isolation process. The in situ processing chamber is adapted for thermal oxidation and etching processes to implement the LOCOS isolation structure.

Abstract: One or more detection circuits are provided for determining the operation of a motherboard prior to placing a microprocessor upon that motherboard. The detection circuit determines a particular way in which the motherboard is configured by ascertaining, for example, a power supply voltage and a clocking frequency output from the motherboard. A probe is used, in combination with the detector circuits, to determine motherboard operation at a socket to which, for example, a microprocessor can be coupled. Jumpers or switches upon the motherboard can be readily found by activating a switch and looking for a response upon the detection circuit output. If a response is not found, the jumper or switch is returned, and another jumper or switch is activated. Once the jumper or switch used for changing system clock speed and/or processor voltage is located, then a display is read as to those parameters to ensure the parameters match the processor specification.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract: One or more detection circuits are provided for determining the operation of a motherboard prior to placing a microprocessor upon that motherboard. The detection circuit determines a particular way in which the motherboard is configured by ascertaining, for example, a power supply voltage and a clocking frequency output from the motherboard. A probe is used, in combination with the detector circuits, to determine motherboard operation at a socket to which, for example, a microprocessor can be coupled. Jumpers or switches upon the motherboard can be readily found by activating a switch and looking for a response upon the detection circuit output. If a response is not found, the jumper or switch is returned, and another jumper or switch is activated. Once the jumper or switch used for changing system clock speed and/or processor voltage is located, then a display is read as to those parameters to ensure the parameters match the processor specification.

Abstract: A two-level cascaded round robin arbiter. The arbiter arbitrates between a plurality of requesters for a shared resource in a round robin fashion. The arbiter comprises a series of first level arbiters which each receive a group of the plurality of requesters and select one requester in each group in a round robin manner. The first level arbiters operate in parallel to select their one requester thereby improving the overall selection time. The first level arbiters provide their selected requester to a second level arbiter which selects one group's selected requester to award use of the shared resource. The second level arbiter selects from among the groups in a round robin manner subject to an indication of a wrap condition provided by each of the first level arbiters to the second level arbiter.