Abstract: A solid state disk (SSD) device includes a non-volatile storage module (NVSM), a secondary power source coupled to power inputs of the SSD, a volatile memory (VM), a controller in communication with the NVSM and the VM. The controller is operable in a (re)populate mode to (re)populate data stored in the NVSM to the VM when primary power is initially applied to power inputs of the SSD and further operable in a primary power on mode to replicate data to the NVSM that was written to the VM in response to received I/O requests while primary power is applied to the power inputs of the SSD. The secondary power source can be decoupled from the power inputs of the SSD while the controller is operating in either the (re)populate mode or the primary power on mode.

Abstract: The storage capacity of a solid state disk (SSD) device is increased through data compression. The SSD is coupled to a host computer system and includes a non-volatile storage module (NVSM) and a volatile memory (VM). The SSD is associated with a predetermined compression ratio of n to 1, where n is a value greater than 1. A virtual storage capacity is initially reported to the host computer system that is n times the physical storage capacity of the VM. An overflow buffer is established on the storage media of the NVSM. The currently available virtual capacity of the VM is monitored based on the current compression ratio and the amount of data currently stored therein. Data is stored to the overflow buffer whenever the available virtual capacity falls below that necessary to successfully process a pending storage operation requested by the host computer system. The data stored in the overflow buffer is populated to the VM when the amount of available virtual capacity of the VM can accommodate the data.

Abstract: A make-up assembly and process provides a true power-tight connection between a first and second tubular segment. Each of the segments has an externally threaded male member at one end and an internally threaded female member at the other end. The male member of the first segment is inserted into the female member of the second segment. A primary torque component is applied to the first segment to engage the external threads of the first segment with the internal threads of the second segment and to advance the male member of the first segment into the female member of the second segment. The value of the primary torque component is monitored. An impulse energy component is then superimposed on the primary torque component when a predetermined onset threshold has been reached. Application of one or both of the primary and impulse energy components is discontinued when a predetermined maximum threshold has been reached.

Abstract: A method of and apparatus for digitally generating a broadband signal comprising a plurality of CW or quadrature modulated signals having incrementally related frequencies wherein said plurality of signals are centered about a center RF frequency is disclosed. The invention provides for generating a first and second composite baseband signal each comprising a linear combination of N sinusoids, or N modulated signals each modulated in quadrature so as to achieve a desired instantaneous phasor value for each of the RF signals. The invention further provides for modulating in quadrature the first and second composite baseband signals on a local oscillator signal having a frequency equal to the center RF frequency.

Abstract: A method for measuring composite distortion levels using a coherent multicarrier RF signal generator having incrementally related frequencies is disclosed. The invention provides for the use of a coherent multicarrier signal generator that permits arbitrary RF carrier phase control on an individual carrier basis in order to enable sequential distortion measurements under varying carrier phase conditions. In order to obtain measurement results that match those obtained by the use of prior art non-coherent signal sources, the present invention provides for averaging of distortion measurement results over a ‘phase configuration ensemble’ that is obtained by multiple sequential measurements, in which the individual carrier phases for each measurement are preselected at random.

Abstract: An apparatus for centering the frequency of an injection locked oscillator (ILO) measures the difference of the phase (or a parameter related to the phase) between ILO output signals in response to alternate high level and low level RF drive signals, and can tune the center frequency of the ILO in accordance with the measurements to minimize the phase difference.

Abstract: A series tuned resonator circuit topology permits implementation of narrow band-pass filters having higher loaded quality factors (QL) and lower insertion loss than was previously achievable in the prior art employing such a topology. The topology employs an additional parallel capacitor for the series-tuned topology, with very low C/L ratios to achieve the combination of higher values of QL, low insertion loss and a steeper roll-off between the pass-band and the stop-band (at both lower and higher frequencies). Air coils are used to achieve the large inductor values desirable for the series-tuned topology.

Abstract: When an atomic instruction executed by a computer processor locks a memory location, the locking is performed before the processor has determined whether the instruction is to be executed to completion or canceled. The memory location is unlocked whether or not the instruction will be canceled. Since the locking operation can occur before it is known whether the instruction will be canceled, the reading of the memory location can also occur early, before it is known whether the instruction will be canceled.

Abstract: Parallel and series tuned resonator circuit topologies are disclosed that permit implementation of narrow band-pass filters having high loaded Q and optimal coupling (for low insertion loss) at frequencies in approximately the 50 MHz to 1 GHz. The topologies employ an additional series capacitor for the parallel-tuned topology, and an additional series capacitor for the series-tuned topology, the capacitors having values counterintuitive to those of skill in the art to produce 6th order transfer functions out of what were once lower order resonators. Multistrip transmission lines are exploited in the parallel-tuned circuit to reduce the inductance of the resonators to achieve a very large skew in the ratios of inductance to capacitance, to increase Q while maintaining optimal coupling between the resonators of the tuned resonator circuits. Air coils are used in the series-tuned topology to achieve the large inductor values desirable for this topology.

Abstract: A multichannel television access control system is disclosed wherein processing of the broadband signal is performed by gated coherent RF injection on a plurality of channels, thereby effecting selective descrambling of an arbitrary subset of channels in a channel group. The system provides for a closed loop injection signal phasor control so as to maintain substantially constant relationship between the television signals and the injected signals. The combined signals are supplied to subscribers enabling the use of their cable ready equipment.

Abstract: The method of the present invention achieves a desired assignment of the physical cell slots comprising a time division multiplexed frame to embedded channels by ascribing an element address to uniquely identify each of the cell slots of the frame. A logical assignment of the cell slots of the frame is made to the embedded channels to be established between one or more specific data sources and sinks. A transform chosen to produce a particular distribution of assignments is then applied to the set of element addresses to produce a set of cell slot addresses, each of which uniquely identifies each cell slot of the frame by its relative physical position within the frame. Each of the element addresses (used to logically associate a cell slot with a channel to be established) is uniquely linked on a one-to-one basis with one of the set of cell slot addresses (used to identify relative position of a cell slot within the frame) through the predetermined transform.

Abstract: An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.

Abstract: A multichannel television access control system is disclosed wherein processing of the broadband signal is performed by gated coherent RF injection on a plurality of channels, thereby effecting selective descrambling of an arbitrary subset of channels in a channel group. The system provides for a closed loop injection signal phasor control so as to maintain substantially constant relationship between the television signals and the injected signals. The combined signals are supplied to subscribers enabling the use of their cable ready equipment.