Abstract: A method of decoding Huffman-encoded words at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for odd numbered code and one for even numbered code, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word per clock cycle.

Abstract: A circuit for decoding one non-zero JPEG encoded pixel per clock cycle, the coded word being of variable length. For a pixel with leading zeros, a two stage pipeline is used, the first stage having one adder for calculating an delta value between the smallest number the variable length portion could be and the actual value, the second stage being an adder for adding the delta value to a base address to generate an address for a look up table, the output being the decoded value. This takes two clock periods to decode a pixel having at least one leading zero. For the Huffman code portion of encoded pixels with no leading zero's, only ten versions of which exist, a gate array for each is provided. Each detects one version and outputs the decoded Huffman code data in one clock cycle. A multiplexer then either selects the decoded data with no leading zero's in one clock cycle or the data with at least one leading zero in two clock cycles.

Abstract: A circuit for decoding Huffman-encoded words describing color pixels in the Lab color space at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for coded L words and one for a and b words, each set of a and b words encoded into one Huffman code word, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word, either L or ab, per clock cycle.

Abstract: A method for increasing the speed of color conversion from a plurality of color spaces to a single color space by reducing the number of color pixels by a factor of two prior to the color conversion step. This pixel reduction constitutes a lossy data compression scheme which takes advantage of the advance knowledge that the pixels will later undergo anti-aliasing by averaging subsequent to the color conversion. First the pixels are grouped into pairs, and one pixel of each pair is eliminated to form a pseudo halfpixel. The eliminated pixel is replaced with a tag identifying either the previous, current or next pseudo halfpixel. Then each pseudo halfpixel is color converted. Finally the indicated previous, current or next pseudo halfpixel, now color converted, is averaged with the current pseudo halfpixel to form a halfpixel, which is then averaged with the halfpixel above or below it to form an anti-aliased full pixel which can be displayed.

Abstract: In a printer for printing text of one color over a background of another color, a method and circuit for allowing the text character outline boundaries to pass through the color halftone dots, creating partial dots in the process, the partial dots within the character boundaries being of the color of the text, and the partial dots outside of the character boundaries being the color of the background. To use a numerical example, to produce an eight bit output dot through which a boundary passes, fifteen halftone bits in the first color are produced for each dot clock, and the rightmost seven bits are latched for the next cycle. On the next clock, fifteen bits are produced, and the leftmost 7 are aligned with the latched seven. If the bits are to the left of the boundary, bits from the first cycle are output, and if the bits are to the right of the boundary, bits from the second cycle are used.

Abstract: This invention is a method of representing the text in a document in a way that enables very fast text processing on digital computers. More specifically, each word of text is represented as a number (or token) that refers to an information packet describing the word's characteristics. Operations then process each token, rather than each character, to perform text processing functions. In addition to the compact nature of this representation, the performance of virtually all functions in a WYSIWYG editor which are dependent on line-breaking speed are improved.

Abstract: In a circuit for rotating a digital image any multiple of ninety degrees, an addressing method which reduces the number of address lines required. The rotation circuit relies on a memory configuation which can access each image pixel in memory individually, and this normally requires a large number of address lines. This invention takes advantage of the periodic nature of the data being accessed to reduce the number of address lines required.

Abstract: Bichromal balls have two hemispheres, typically one black and one white, each having different electrical properties. Each ball is enclosed within a spherical shell and then a space between the ball and shell is filled with a liquid to form a microsphere so that the ball is free to rotate in response to an electrical field. The microspheres can then be mixed into a substrate which can be formed into sheets or can be applied to any kind of surface. The result is a film which can form an image from an applied electrical field.

Abstract: This circuit for serializing n parallel data bits requires that the data clock, having a clock period T, be used to generate n phased clocks of the same frequency as the data clock, but varying in phase such that each phased clock is delayed T/n with respect to the previous one. This can be done using a digital phase locked loop device. These n phased clocks and n parallel data bits are then input to a logic circuit which uses an n input Register and an n input multiplexer to output one data bit for each phased clock. The result is a serializer that converts parallel data to serial data without the need for generating a higher frequency clock.

Abstract: A process of loading an image in the form of a bit map into a memory which can transfer data words in burst mode in either row or column direction. First, the memory is divided into two sections with odd words stored in one section, even in the other, which allows ping pong buffers to be reading one word from memory while the next is being accessed. Also, the page height is set to be an odd number of words. Therefore, when the entire page is read in or out, successive words in either the row or column direction will always be alternately odd and even. If a partial image is read into the memory, this odd and even relationship will also hold. If an image with an even number of rows is read in, in order to preserve the sequential odd-even sequence, in every other column of the original data successive words are swapped so that the word order becomes 1, 0, 3, 2, etc. Then the addresses are also generated in staggered order, so that the words go into the correct location in memory.

Abstract: A system for changing the source and destination devices of data transfers under software control. Default data transfers are made from numbered source devices to the same-numbered destination devices, the data requests being routed through multiplexers which pair, for example, source 1 with destination 1, source 2 with destination 2, etc. The multiplexer control signals originate in a register which is originally loaded with default control bits. However, in real time, the bits within the control register can be re-loaded to provide outputs other than the default values. Then, the data from a source can be directed to any one of the destination devices.

Abstract: A protocol for communication through a bus controller to control data transfers between a host processing platform and the data bus of a bit map printer. This protocol is optimized for a data bus which connects a number of ASIC accelerator cards in addition to the printer, disk controller, bus controller and other typical system cards. The basic data transfer cycle transfers eight data words on the bus between ASIC's, I/O devices, printer and any other devices.

Abstract: A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.

Abstract: In a xerographic image, where a darker area is separated by a lighter area across a sharp boundary, there is an edge enhancement effect where there will be a black outline around the darker area and a white outline around the lighter area. In x-ray mammography, the effect is that the skin line will be darkened for a positive image and lightened for a negative image, and a loss of detail at the skin line will result. To increase visible detail at the skin line without increasing the radiation, a recharging scorotron can be used between the imaging and toner stations to recharge back to a low level of charge only those areas of the latent image that have been fully discharged. All other areas are allowed to remain unchanged. The result is a reduction of skin line deletions at a reduced x-ray exposure. Such a scorotron, in the shape of a box around the corona wires, can be constructed using a conductive top, insulative sides and a screen bottom.

Abstract: A method is described for determining readiness of devices in a digital data bus system to transfer data signals. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lines for communicating data signals, and control lines for communicating control signals. The bus system also includes a plurality of devices. Each device is connected to the bus and has an address on the bus. At least one device is a source device capable of sending data signals and at least one device is a destination device capable of receiving data signals. A bus controller connects to the bus and controls the bus. The control lines include bus request lines that connect each device to the bus controller for communicating a bus request signal from a device to the bus controller. The bus request signal indicates that the device is ready to send or receive data signals.

Abstract: A circuit to be used just prior to the printing engine to improve the image quality of a raster output scanner by modifying the darkness, size or shape of the spot. A buffer holds a window of n by n image pixels, and compares the bit pattern to a set of templates. For each match, a correction number is output, each correction number being a gray scale, duty cycle or bit pattern to be used to correct the center pixel of the current window. The comparison logic, instead of comparing the entire set of bits in the window to the templates, uses a number of small logic blocks in parallel, each comparing a subset of bits from the window. The output from this first set of comparisons is substantially reduced from the original set. This reduced set is now input to a second logic block which generates the final correction output bits.

Abstract: A faster method of generating a mask stroke for a given trajectory. The first step is to determine if parallel lines can be developed for the entire trajectory. If not, the trajectory is divided into segments for each of which a set of parallel lines can be generated. The second step is to generate the parallel lines.

Abstract: A printer for printing on envelopes. The envelope is fed into the printer bottom edge first, the flap is opened with the glue side of the flap opposite the developing and fusing stations in the printer. This arrangement allows printing of addresses on the envelope body and flap, and also avoids contaminating the fuser and developing stations with glue.

Abstract: An x-ray photoreceptor for use in a xerographic system having a high arsenic layer 5 to 40 microns in thickness between the substrate and the selenium layer for trapping positive charge injected from the interface. Since this positive charge otherwise tends to discharge a negatively charged plate, the provision of this trapping layer will allow the plate to be used for either positive or negative charging.

Abstract: A FET which can be formed on a silicon substrate and which can operate in the enhancement mode. The n+ source and drain are centrally located within n-wells which extend under the gate area, and are separated by a distance. By appropriately choosing the distance between n-wells, different threshold voltages can be obtained for several transistors on the same chip.