Abstract: According to some embodiments, a method, system, and apparatus to provide thermal management control. In some embodiments, the method includes receiving, by a control mechanism, a plurality of temperature representative signals from a plurality of temperature sensors, receiving a command signal from the control mechanism by an output weighting matrix mechanism, and controlling at least one thermal cooling device with at least one weighted output signal from the output weighting matrix mechanism.

Abstract: In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed.

Abstract: In some embodiments an interconnect includes a waveguide and a transmission line coupled in parallel with the waveguide. Other embodiments are described and claimed.

Abstract: In some embodiments, a cooling device may be mounted to a portion of a chassis of an electronic system, wherein the cooling device may be releasably and pivotably attached to the chassis in at least an open position to permit access to components within the electronic system and a closed position to permit installation of a cover on the chassis. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, a cooling device may be mounted to a portion of a chassis of an electronic system, wherein the cooling device may be releasably and pivotably attached to the chassis in at least an open position to permit access to components within the electronic system and a closed position to permit installation of a cover on the chassis. Other embodiments are disclosed and claimed.

Abstract: In some embodiments a power circuit includes a driver output, a MOSFET, and circuitry to ensure a full and fast positive drive to a gate of the MOSFET when the driver output goes to a high signal level, and to ensure a full and fast low negative drive to the gate of the MOSFET when the driver output goes to a low signal level. Other embodiments are described and claimed.

Abstract: In some embodiments an apparatus includes a higher order statistical signal processor to process a jittered digital signal, a diagonal line average unit to identify a distinct line in a signal output from the higher order statistical signal processor, and a peak detection unit to determine a peak value in response to an output of the diagonal line average unit and to provide a data rate signal as an output. Other embodiments are described and claimed.

Abstract: In some embodiments it is determined if a speed of a Universal Serial Bus cable of greater than 480 Mb per second is supported at each end of the Universal Serial Bus cable, the length of the Universal Serial Bus cable is calculated, and the speed of the Universal Serial Bus cable is increased beyond 480 Mb per second in response to the determining and the calculating. Other embodiments are described and claimed.

Abstract: In some embodiments an indication of an intended use of a logic device is stored in a register of the logic device, and any further programming of the register is prevented. Other embodiments are described and claimed.

Abstract: In some embodiments, a heatsink includes a thermally conductive core and at least ten thermally conductive fins extending quasi-radially from the thermally conductive core, wherein most of the fins are of uniform length, and wherein at least a portion of the thermally conductive core is shaped such that the fins having uniform length form a substantially rectangular cross sectional form factor. Other embodiments are disclosed and claimed.

Abstract: A voltage regulator provides an operation voltage to a memory system and a transient voltage supply adjusts the operation voltage provided by the voltage regulator during transient events of the memory system.

Abstract: In some embodiments a channel is formed in printed circuit board material, the formed channel is plated to form at least two side walls of an embedded waveguide, and printed circuit board material is laminated to the plated channel. Other embodiments are described and claimed.

Abstract: Arrangements facilitating ordered transactions, e.g., ordered writes, in a packet switch system having multiple switch elements.

Abstract: In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.

Abstract: In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Abstract: In some embodiments, an circuit card includes an electronic circuit substrate, a ground plane on the electronic circuit substrate, first and second differential signal pads on the electronic circuit substrate, a ground return signal pad associated with the first and second differential signal pads, the ground return signal pad being connected to the ground plane on the electronic substrate, and a cutout structure on the ground plane positioned near a location where the ground return signal pad connects to the ground plane, wherein the cutout structure is configured to direct a ground return path associated with the first and second differential signal pads to the ground return signal pad associated with the first and second differential signal pads. Other embodiments are disclosed and claimed.

Abstract: In some embodiments an expected value is compared with a number of times a storage device has been powered up and/or spun up. A cache disassociation is detected in response to the comparing. Other embodiments are described and claimed.

Abstract: In some embodiments, a frequency dependent gain circuit is coupled to an output of an amplifier. The gain circuit provides at least two ranges of frequency dependent gain characteristics in response to the output of the amplifier. A control circuit provides one of the at feast two gain values as an output. Other embodiments are described and claimed.

Abstract: In some embodiments, a receiver can receive from an interconnect information packets and idle packets, where one or more of the idle packets includes a test pattern. A condition detector can detect a condition of the interconnect in response to the test pattern. Other embodiments are described and claimed.

Abstract: In some embodiments, a comparator compares an incoming memory address with a memory address currently being copied by a memory copy operation. A holding buffer holds the incoming address prior to forwarding it to a memory read/write queue if the incoming memory address is the same as the memory address currently being copied by the memory copy operation, forwards the buffered incoming memory address to the read/write queue once the memory copy operation for the memory address currently being copied has finished. Other embodiments are described and claimed.