Abstract: In an on-board sensible signal that is activated by the speedometer of a vehicle when the vehicle speed exceeds a predetermined threshold and that remains activated when the speed is reduced below this threshold, the improvement consists of a combination of timing and logic circuitry that deactivates the signal when and only when the vehicle stops and remains at rest for a predetermined period of time.

Abstract: Speed data samples from an ordinary digital speedometer are written sequentially into a number of addressed memory locations. Each new entry replaces the oldest entry then in memory. This writing process occurs only when the vehicle is moving, so the memory cannot be erased when the vehicle is at rest. The last writing address used is retained. Any stored data sample may be recalled and displayed by presenting its address. The time-before-vehicle-stop of the displayed recalled data corresponds to the sequential interval between the recalling address and the last-used writing address. In the most convenient modification, the user stepwise specifies the sequential interval and the device produces the appropriate recalling address.