Abstract: Integrated stacked microchannel heat exchanger and heat spreaders for cooling integrated circuit (IC) dies and packages and cooling systems employing the same are disclosed. In one embodiment, a stacked microchannel heat exchanger is operatively and thermally coupled to an IC die or package using an interstitial solder or a solderable material in combination with solder. In another embodiment, a stacked microchannel heat exchanger is operatively and thermally coupled to an IC die or package using an adhesive. In a further embodiment, a stacked microchannel heat exchanger is operatively coupled to an IC die or package by fasteners and is thermally coupled to the IC die or package using a thermal interface material. The integrated stacked microchannel heat exchanger and heat spreaders may be employed in a closed loop cooling system including a pump and a heat rejecter.
December 31, 2003
Date of Patent:
October 3, 2006
Ven R. Holalkere, Ravi Prasher, Stephen Montgomery
Abstract: Briefly, in accordance with one embodiment of the invention, a method of using hue to interpolate color pixel signals includes the following. For a particular pixel location in a subsampled color image, differences in hue are compared for two mutually orthogonal directions across the particular pixel location. A color signal value for that particular pixel location for a color plane other than the color plane of the pixel signal value in the subsampled color image of that location is computed. The computation includes relatively weighing the differences in hue values, the relative weights depending, at least in part, on the difference in hue value in one direction relative to the other.
Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.
December 31, 2001
Date of Patent:
April 25, 2006
Josh B. Mastronarde, Aditya Sreenivas, Thomas A. Piazza
Abstract: Implementations of a progressive two-dimensional pyramid filter bank are disclosed including a method of adding a first and a last input signal sample to a sum of input samples of a next lower-tap filter of a current filter to produce a sum of input signal samples for the current filter; and adding the sum of input signal samples for the current filter to an output signal sample of the next lower-tap filter of the current filter to produce an output signal sample for the current filter. In one implementation the first and second adding is performed by different adders. In another implementation the first and second adding is applied by column and by row.
Abstract: Embodiments of the present invention provide a method and apparatus for handling memory refresh and maintenance operations for graphics and other applications. In particular, refresh and memory operations are executed in two stages. A first stage includes, but is not limited to, memory channel temperature calibration, RAC auto current calibration, and RAC auto temperature calibration. First stage operations are scheduled when the primary display is not requesting data from memory, such as when the display is in its vertical blanking interval. A second stage includes, but is not limited to, memory refreshes and memory current calibration. These operations are scheduled when there are no display streams (primary and secondary) or when display is requesting in a low priority mode.
Abstract: Firmware for a computer system reduces boot time utilizing the multi-tasking capabilities of a processor to perform at least two boot tasks simultaneously. The boot tasks can be divided into groups which are executed in parallel. To accommodate certain boot tasks which must be performed in sequence, the boot tasks can be arranged in groups which are executed sequentially. The tasks within each group are performed simultaneously. The boot time is also reduced by only enumerating hardware if the system hardware has been changed since the previous boot. The firmware determines if hardware has been changed by checking an electrical hardware latch which signals whether the computer case has been opened.