Abstract: This invention extends the coverage and improves the capacity of wireless communication networks using relay nodes. The relay nodes are wirelessly connected to the base station. The base station uses the same radio access technology for a link between the base station and user equipment and between the base station and the relay node. The relay node uses the same radio access technology for a link between the base station and the relay node and between the relay node and the user equipment. The relay node supports at least a Physical Layer (PHY), a Medium Access Control (MAC) sub-layer and a Radio Link Control (RLC) sub-layer protocol.

Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.

Abstract: This invention is a method to automatically configure the universal variable length coding (UVLC). The method is applicable to code the syntax elements with a lot of symbols like the transform coefficients and motion vectors. The configuration problem includes a configuration method based on a genetic algorithm (GA). The method can be applied to on-the-fly configuration of codewords during video encoding, or to off-line training of code tables. This invention also includes several techniques to reduce the required operations for applications which have only limited processing power.

Abstract: The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447, 450, 452) by a central pipeline is the medium for all data communications among DSP clusters (455), external devices, and external memory. A transfer request queue manager (420) receives, prioritizes and queues data transfer requests. Each data port includes an identically configured interior interface (901) connected to the hub (435) and an exterior interface (902) configured for a target external memory/device connected to the port. The interior interfaces of all ports are clocked at a common internal frequency, while the exterior interfaces are clocked at the frequency of the external memory/device connected to the port.

Abstract: A pipelined microprocessor (10) and system (2) incorporating the same, utilizing combined actual branch history and speculative branch history to predict branches, is disclosed. The microprocessor (10) includes a branch target buffer, or BTB, (56) having a plurality of entries (63) that are associated with previously branching instructions. Each entry (63) has a tag field (TAG) for storing an identifier for its branching instruction based upon the logical address therefore, and a target field (TARGET) for storing the target address for the branching instruction if the branch is taken. Each entry (63) also includes a branch history field (BH), the most-recent bits of which are applied to a pattern history table, or PHT, (53) as an index thereto to retrieve a prediction for the branch.

Abstract: A ring antenna (10) for resonant circuits for identifying metallic containers has an annular core (11) having at least one core surface (11a') corresponding to at least one surface of the container and made from ferrite. The core may be U-shaped, having a base portion and a first and second arm portions, or L-shaped, having a base portion and a first arm portion (11a). The antenna (10) also has a copper wire coil (12) wound around a first portion of the core; and an aluminum shield (13) affixed to the at least one core surface (11b') and separating the core from the surface of the container. Further, a interrogation system for identifying metallic containers includes the ring antenna (10) coupled to a resonant circuit (86) included in a transponder or a reader.

Abstract: A static antenna tuning and antenna voltage measurement circuit (40) includes antenna voltage conversion circuitry (44) for converting a voltage signal (42) to a measurement signal representative of transmitter/receiver antenna (16) operation. Voltage signal (42) arises from transmitter/receiver antenna (16) transmitting or receiving a recognition signal (S1, S2). Comparator circuitry (48, 50, 52) compares the measurement signal to a predetermined optimal transmitter/receiver antenna operation signal.

Abstract: Circuitry 10 is provided that contains two (or more) PLA matrix structures 12, 14 which share at least some outputs and are interconnected with a common output structure 18, individual input 30 and output 42, 62 structures, and an appropriate controller 28 for selecting which PLA matrix structure 12, 14 is to be employed. A common input structure 16 may be interconnected with the PLA matrix structures 12, 14 employed. The controller 28 may also be employed to power-down the PLA matrix structures not employed. The controller 28 may be static and select one matrix structure until reset, or dynamic and change as a function of some control signal.

Abstract: A Flash EEPROM memory array includes a plurality of transistor memory cells (24) arranged in rows and columns. The sources of the transistors (24) are connected to Virtual Ground Lines (29) and the drains thereof are connected to Column Lines (28). The memory cells (24) are programmable by Fowler-Nordheim tunneling. Each cell also includes an isolation structure having a first isolation tank of the first conductivity type material for surrounding each of the floating gate transistor memory devices and a second isolation tank of a second conductivity type material opposite to the first conductivity type surrounding the first isolation tank, allowing application of a negative voltage to the source or drain of the cell. Initially, all of the transistors are erased in the FLASH ERASE operation by disposing the Word Lines at a negative medium voltage and the Bit Lines at a positive medium voltage. Thereafter, selected transistors can be written to by selectively charging the floating gates in the transistors.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored In a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first data register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferably stored in another data register.

Abstract: An electronic half adder circuit wherein an entire word of either 16 or 32 bits is divided into stages, carry is rippled within each stage and look-ahead carry is computed between the stages, having a dual gate look-ahead carry circuit for propagating a look-ahead carry bit between said stages. This is also a processor system. The system includes: memory for storing program instructions; a processor coupled to the memory for receiving predetermined ones of the program instructions; the processor comprises: an arithmetic unit; control circuitry for controlling the arithmetic unit in response to selected ones of the predetermined program instructions; a counter coupled to the control circuitry comprising half adder circuitry wherein a dual gate look-ahead carry circuit for propagates a look-ahead carry bit between the stages.

Abstract: The present invention is a graphics data processor which includes the capability of determining whether a defined pixel location in a graphics display is within a window in an X Y coordinate system. The respective X and Y coordinates of the selected pixel are separately compared with the window limits. The window limits are preferable expressed as the X and Y coordinates of two diagonally opposite vertexes of a rectangular window. The results of this comparison are preferable available in two forms. In a first embodiment a single data processing instruction enables the generation of a digital data word which indicates the relation of the pixel to the window. This digital word includes a separate indication of the relationship of the pixel to the vertical and horizontal window limits. This indication can be used to generate a "trivial rejection" in determining whether a line or line segment passes through the window by ANDing the results for two points on the line.

Abstract: A speech recognition system includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.

Abstract: An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector.

Abstract: A system for real-time digital processing of a video signal using a large number of one-bit serial processor elements each of which operates on one pixel of a horizontal scan. The video signal is converted to digital by an A-to-D converter, and stored in a set of input registers, one register for each processor element. All of these input registers are loaded during a horizontal scan, as the input registers are addressed in sequence by a commutator. Each processor element includes a one-bit binary adder, a set of one-bit registers, and two one-bit wide data memories of a size to store data from several scans. The processor elements are all controlled in common by a sequencer, a state machine or a processor. The processed video data is transferred to an output register for each processor element, from which it is converted to a video signal by a D-to-A converter.

Abstract: An electromechanical apparatus includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A modem includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register.

Abstract: A graphics data processing apparatus having graphic image operations on two images. Two graphic images are formed into a single combined image based upon a predetermined combination of the multibit color codes representing corresponding pixels of the two images. A transparent color code is permitted for the first of the graphic images. The combination of a transparent color code from the first graphic image with any color code from the second graphic image yields the color code of the second graphic image. This innovation enables the use of color codes having selectable numbers of bits set by the number stored in a pixel size register. In particular the transparent color code, which is detected by a transparent color code detection device independent of the image operation, has a selectable number of bits set by the pixel size register in a manner like any other color code.