Abstract: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.

Abstract: A method of selectively depositing a ferroelectric thin film on an indium-containing substrate in a ferroelectric device includes preparing a silicon substrate; depositing an indium-containing thin film on the substrate; patterning the indium containing thin film; annealing the structure; selectively depositing a ferroelectric layer by MOCVD; annealing the structure; and completing the ferroelectric device.

Abstract: A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

Abstract: A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

Abstract: In a wireless communication device which is transportable between plural geographic region, wherein each geographic region has preferred and non-preferred communication systems for the wireless communication device, a method of selecting an appropriate communication system, including providing the wireless communication device with a non-PRL system table for storing acquisition parameters, including a communication system identification, a band class designation for a band class, a channel designation for a channel in the band class, and geographic region identification; making entries in the non-PRL system table when the wireless communication device acquire an appropriate channel in a geographic region; searching the non-PRL system table when the wireless communication device next changes geographic regions; and selecting a communication system based on the acquisition parameters in the non-PRL system table as a result of the searching.

Abstract: A scheduler for providing quality of service in a local area network, wherein the local area network includes a plurality of stations, and wherein data flow moves over the network in superframes, includes a mechanism for governing channel resources in the local area network, including a transmit specification controller for granting a transmit specification to a data flow from one station on the network to another station on the network; and a TXOP mechanism for terminating transmits opportunities for stations which have successfully completed data transmission, thereby changing the length of a superframe.

Abstract: A method of providing a secure clock in a communication device in contact with a communication system includes detecting a clock event whenever a clock event occurs; initializing a secure clock and setting a secure clock flag to TRUE; and setting the secure clock to a secure clock time. A secure clock mechanism for use in a communication device which is in contact with a communication system includes real-time clock hardware; programmable memory and non-volatile memory; and a back-up battery for powering the secure clock mechanism; a clock event detection mechanism for detecting clock events, which are taken from a group of clock events consisting of user clock events and system clock events; a secure clock initializing mechanism for setting the secure clock and for setting a secure clock flag to TRUE; and a secure clock setting mechainism for setting the secure clock to a secure clock time.

Abstract: Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatably with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit for generating a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

Abstract: A method of forming PrXCa1-xMnO3 thin films having a PMO/CMO super lattice structure using metalorganic chemical vapor deposition includes preparing organometallic compounds and solvents and mixing organometallic compounds and solvents to form PMO and CMO precursors. The precursors for PMO and CMO are injected into a MOCVD chamber vaporizer. Deposition parameters are selected to form a nano-sized PCMO thin film or a crystalline PCMO thin film from the injection of PMO and CMO precursors, wherein the PMO and CMO precursors are alternately injected into the MOCVD chamber vaporizer. The selected deposition parameters are maintained to deposit the PCMO thin film species having a desired Pr:Ca concentration ratio in a specific portion of the PCMO thin film. The resultant PCMO thin film is annealed at a selected temperature for a selected time period.

Abstract: A method of CaO-doped SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition, includes preparing a wafer to receive a spin-coating thereon; selecting metalorganic compounds to form a SrCu2O2 precursor, mixing and refluxing the metalorganic compounds to form a precursor mixture; filtering the precursor mixture to produce a spin-coating precursor; applying the spin-coating precursor to the wafer in a two-step spin coating procedure; baking the spin-coated wafer using a hot-plate bake to evaporate substantially all of the solvents; and annealing the spin-coated wafer to form a CaO-doped SrCu2O2 layer thereon.

Abstract: A method of fabricating a silicon integrated circuit on a glass substrate includes preparing a glass substrate; fabricating a silicon layer on the glass substrate; implanting ions into the active areas of the silicon layer; covering the silicon layer with a heat pad material; activating the ions in the silicon layer by annealing while maintaining the glass substrate at a temperature below that of the thermal stability of the glass substrate; removing the heat pad material; and completing the silicon integrated circuit.

Abstract: A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 ? to 1 ?m below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.

Abstract: A method of selective etching a metal oxide layer for fabrication of a ferroelectric device includes preparing a silicon substrate, including forming an oxide layer thereon; depositing a layer of metal or metal oxide thin film on the substrate; patterning and selectively etching the metal or metal oxide thin film without substantially over etching into the underlying oxide layer; depositing a layer of ferroelectric material; depositing a top electrode on the ferroelectric material; and completing the ferroelectric device.

Abstract: A method of fabricating a germanium film on a silicon substrate includes preparing a silicon substrate; depositing a first germanium film to form a continuous germanium film on the silicon substrate; annealing the silicon substrate and the germanium film thereon in a first annealing process to relax the germanium film; depositing a second germanium film on the first germanium film to form a germanium layer; patterning and etching the germanium layer; depositing a layer of dielectric material on the germanium layer; cyclic annealing the silicon substrate having the germanium layer and dielectric material thereon; and completing a device containing the silicon substrate and germanium layer.

Abstract: A coding scheme for use with a CSMA protocol to enable transmission of high data rate information signals thereover, wherein the protocol includes an OFDM physical layer, a MAC layer and a CSMA protocol inner code, includes providing an outer coding generator; generating outer code words containing coded and uncoded data therein in the outer code generator; wherein, the generated outer code words fit with a small multiple of data bits with an OFDM symbol having a fixed number of data bits, thereby providing for transmission of high data rate information using the outer code and the CSMA protocol inner code at a data rate of at least 24 Mbps and at a packet error rate of less than 1.5·10?9.

Abstract: A method of clearing an internal print queue in a print output device includes processing a print job in a print output device to make a processed print job; storing the processed print jobs in the internal print queue of a print output device; detecting an overload condition in the internal print queue; determining which processed print jobs are not ready to be physically printed; selecting at least one not ready to be printed processed print job in the internal print queue for transfer out of the internal print queue to clear the overload condition; moving the selected processed print job to a temporary storage print queue; and moving the selected processed print jobs from a temporary storage print queue to the internal print queue upon occurrence of a predetermined event.

Abstract: A method of forming a substrate for use in IC device fabrication includes preparing a silicon substrate, including doping a bulk silicon (100) substrate with ions taken from the group of ions to form a doped substrate taken from the group of doped substrates consisting of n-type doped substrates and p-type doped substrates; forming a first relaxed SiGe layer on the silicon substrate; forming a first tensile-strained silicon cap on the first relaxed SiGe layer; forming a second relaxed SiGe layer on the first tensile-strained silicon cap; forming a second tensile-strained silicon cap on the second relaxed SiGe layer; and completing an IC device.

Abstract: A method of determining colorant amounts to be laid down in a color printer includes determining an initial set of cyan, magenta and yellow (CMY) values; ordering the initial set of CMY values to determine the largest, middle and smallest values of the three values and generating an ordering vector; selecting a gamut center black generation LUT and two gamut boundary black generation LUTs from a set of black generation LUTs from a selection table; indexing the selected black generation LUTs to determine black values for each black generation LUT as a function of the minimum of the CMY values; interpolating a final output black colorant amount from the black values, and interpolating final output CMY colorant amounts from the initial set of CMY values, the maximum CMY ink limit constraint, and a set of boundary threshold values.

Abstract: A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1?xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1?xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1?xGex layer; trench etching of the top silicon and Si1?xGex, into the silicon substrate to form a first trench; selectively etching the Si1?xGex layer to remove substantially all of the Si1?xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1?xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

Abstract: A method of fabricating and programming a ferroelectric memory transistor for asymmetrical programming includes fabricating a ferroelectric memory transistor having a metal oxide layer overlaying a gate region; and programming the ferroelectric memory transistor so that a low threshold voltage is about equal to the intrinsic threshold voltage of the ferrorelectric memory transistor.