Patents Represented by Attorney Robert E. Rudnick
  • Patent number: 5710711
    Abstract: A method and apparatus are taught which modify digital integrated circuits for partial scan testing and do so with little or no impact on the circuit's performance characteristics. Illustratively, the scan memory elements are selected from among all memory elements in a circuit based on their ability to eliminate feedback cycles in the circuit and on considerations of the potential performance degradation due to the inclusion of scan memory elements. A feedback cycle is defined as a feedback path from the output of a memory element to the input of said memory element.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: January 20, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Kwang-Ting Cheng, Jing-Yang Jou
  • Patent number: 5708389
    Abstract: An integrated circuit employing quantized feedback is capable of compensating for decay in capacitively-coupled digital signals. In an exemplary embodiment, the integrated circuit includes a quantized feedback receiver connected to a capacitively-coupled integrated circuit input. The capacitively-coupled input produces a decaying signal for corresponding intervals of an input digital signal that are substantially DC voltages. Longer sequences of consecutive data bits of the same logic state in the input signal are represented by a corresponding longer DC voltage signals resulting in a greater decay in the capacitively-coupled signal. The receiver operates by generating a complementary feedback signal which is combined with the capacitively-coupled signal. The feedback signal is generated with a magnitude rate of change that compensates for the decay in the capacitively-coupled signal such that the digital information in the combined signal can be detected substantially without error due to the decay.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: January 13, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Thaddeus John Gabara
  • Patent number: 5703581
    Abstract: A data compression technique for encoding a data stream of symbols processes a current sequence of symbols in the stream using an adaptive look-up table containing strings of different lengths by identifying whether a match of a longest string from the table or a shorter string would produce a lower compression ratio by "looking ahead" and identifying a match between a next sequence in the data stream and strings in the table. The compression technique identifies those situations where it is advantageous to use a compressed code identifier for a current sequence that is shorter than the longest matching sequence. Such situations exist when the compression ratio achieved for compressing the current sequence in combination with the next sequence in the stream is greater when other than the longest match is employed for the first sequence. A corresponding decompression technique to decode data encoded using a similar "look ahead" technique is also disclosed.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: December 30, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Yossi Matias, Suleyman Cenk Sahinalp
  • Patent number: 5667132
    Abstract: Solder bonding of first and second contact pad arrays is accomplished by forming contact structures, such as posts with vertical or tapered sides, on the contact pads of the first array and solder bumps on the second array. The respective contact structures should have an average cross-sectional area that is less than the average cross-sectional area of the corresponding solder bumps. The contact structures and solder bumps are then bonded by a bonding process at a temperature and pressure where the solder bumps deform and envelop at least a portion of the respective contact structures. It is possible to employ the contact structures as a compression stop during the bonding process. The temperature should be below the melting points of the contact structures. In this manner, solder bump spreading can be reduced during bonding which correspondingly reduces electrical shorting of adjacent formed interconnect bonds.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: September 16, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Leo Maria Freishyn Chirovsky, Lucian Arthur D'Asaro, Donald William Dahringer, Sanghee Park Hui, Betty Jyue Tseng
  • Patent number: 5646943
    Abstract: An integrated method for congestion control uses access regulator to control the admission of information from a communication device into a network according to a predetermined function characterized by a set of parameters. A node within the network sends a signal indicating a level of congestion in the node to the access regulator, and at least one of the parameters is adjusted in response to the signal. The parameter may additionally be adjusted according to other parameters which are selected according to stability and transient response criteria.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: July 8, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Anwar Elwalid
  • Patent number: 5646543
    Abstract: An integrated circuit output section has a controller that controls a plurality of drivers to transmit data signals over output lines in a group staggered manner to substantially reduce the generation of inductive noise or ground and power bounce. The controller staggers the transmission of the data signals in each group relative to the other groups to achieve a reduction in inductive noise of greater than 25% using relatively short total staggering times of less than five times the transition switching time of a driver for the groups of data signals. Also, an enhanced reduction in inductive noise is achieved with a total staggering time equal to or less than a driver transition switching time, wherein at least one group has a different number of data signals than the other groups.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: July 8, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Attilio Joseph Rainal
  • Patent number: 5623605
    Abstract: The methods and systems of the invention enable connectionless-oriented server and client programs operating on processing systems to communicate with connection-oriented routines operating on different processing systems linked to connectionless or connection-oriented networks by establishing connections or communications virtual circuits between such programs. The connectionless-oriented server and client programs may be modified to communicate with a connection manager to establish a virtual circuit before initiating communications with the connection-oriented routines. The invention further utilizes encapsulators and decapsulators to enable communication programs to transfer data packets in a first format on an established virtual circuit over a network transmitting data in a second format.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: April 22, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Srinivasan Keshav, Rosen Sharma
  • Patent number: 5623499
    Abstract: A method and apparatus for generating a conformance test data sequence of minimal length to verify that a device conforms to a protocol entity which can be characterized by a simplified extended finite state machine. The method generates an expanded directed graph of the protocol wherein each state is represented by a state vertex and a dummy vertex which are connected to other similar state and dummy vertices by directed edges in a configuration corresponding to the operation of the machine. The directed edges are then assigned traversal numbers corresponding to the minimum number of times a respective directed edge need be traversed in order to test values in a predetermined test data set. The traversal numbers of the expanded directed graph are balanced to form a symmetric expanded directed graph. An Euler tour and a corresponding unique input-output sequence of the last state of the Euler tour are generated to form the conformance test data sequence.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: April 22, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Ya-Tien Ko, Sanjoy Paul
  • Patent number: 5623564
    Abstract: A mechanically stable self-aligned optical switch having a low insertion loss is achieved by employing two silica optical structures containing a plurality of waveguides. The waveguides within each structure are arranged in a common plane. It is possible to achieve such silica optical structures by cleaving a monolithic silica optical structure. In one embodiment, the structures are disposed on respective flat surfaces of moveable and fixed bases that are aligned in a common plane. The structures are further positioned with their cleaved edges adjacent to and facing one another. In this manner, the waveguides of the cleaved structures are effectively self aligned in the direction normal to the flat surface of the bases. In operation, the moveable base moves in the direction along the cleaved edges to selectively provide connections between the waveguides in each structure.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 22, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Herman M. Presby
  • Patent number: 5608262
    Abstract: Described is a novel packaging of MCM tiles without wire-bond interconnections and in a total thickness which is reduced relative to conventional MCM packaging. The MCM tile includes a substrate with a plurality of peripheral metallizations and at least one chip flip-chip mounted on the substrate. The PWB is provided with an aperture which is smaller than the size of the silicon substrate but larger than the outside dimensions of the mounted chips. The substrate is positioned on the PWB so that its ends overlap areas of the PWB adjacent the aperture and the chips fit into the aperture. Peripheral metallizations on the substrate are interconnected to metallizations on the PWB by either solder reflow technology or conductive adhesive technology.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: March 4, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Thomas D. Dudderar, Byung J. Han, Alan M. Lyons, King L. Tai
  • Patent number: 5574420
    Abstract: In accordance with the invention, a variety of magnetic devices can be made up of two or more low-profile surface components on a printed circuit board. For example, low profile devices comparable to gapped U-core pair and gapped E-core pair inductors or transformers can be formed of two and three components, respectively, and four components can be assembled into a gapped toroidal transformer or inductor. The components can be made in form for both linear and non-linear inductors.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: November 12, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: Apurba Roy, Steven A. Shewmake, James C. Wadlington
  • Patent number: 5572167
    Abstract: A phase-looked loop circuit with holdover mode is formed utilizing a primary and secondary phase-locked loop circuits. Each loop circuit comprises a phase detector, loop filter, VCXO and frequency divider. The secondary loop is configured such that its output is very stable. The primary loop is phase-locked on a received reference clock signal and the second loop is phase locked on the output of the primary loop. The scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched to a holdover mode where the input of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output of the primary loop is phase-looked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back to the reference clock signal.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: November 5, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: John M. Alder, Hendricus M. H. Bontekoe
  • Patent number: 5483236
    Abstract: The present invention is a reduced iteration decoder circuit and method to compute error-locator sequence values for use in the correction of bit errors in Reed-Solomon or BCH coded information. By utilizing special properties of Reed-Solomon code and BCH codes, the decoder circuit of the present invention can detect n symbol errors using approximately n mathematical iterations with substantially reduced decoding processing time. A further reduction of decoding time is achieved by the performance of a substantial portion of the decoding processing in a parallel manner. The present invention may be utilized in digital communication systems and data storage systems or other information systems where Reed-Solomon or BCH encoding is utilized.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: January 9, 1996
    Assignee: AT&T Corp.
    Inventor: Qi Bi
  • Patent number: 5473696
    Abstract: An improved method and apparatus for encrypting and scrambling information cells transmitted on a telephone system local loop from a central office to a plurality of user premises networks via a shared medium passive optical network. Prior to transmission, the information cell is encrypted for security purposes and scrambled to improve its transmission properties by modulo 2 addition of the information cell and a combined encryption and scrambling sum pattern. At the other end of the passive optical network which is connected to user premises networks, the received encrypted and scrambled information cells are used to generate a processed cell by the modulo 2 addition of the received cell and a combined decryption and descramble sum pattern.
    Type: Grant
    Filed: November 5, 1993
    Date of Patent: December 5, 1995
    Assignee: AT&T Corp.
    Inventors: John H. M. van Breemen, Robert J. M. Verbeek
  • Patent number: 5464664
    Abstract: Applicants have discovered that gallium arsenide surfaces can be dry passivated without heating or ion bombardment by exposing them downstream to ammonia plasma formation. Specifically, a workpiece having exposed gallium arsenide surfaces is passivated by placing the workpiece in an evacuable chamber, evacuating in the chamber, generating an ammonia plasma removed from the immediate vicinity of the workpiece, and causing the plasma products to flow downstream into contact with the workpiece. Preferably the plasma gas pressure is 0.5 to 6.0 Torr, the substrate temperature is less than 100.degree. C. and the time of exposure is in excess of 5 min. The plasma should be generated at a location sufficiently removed from the workpiece that the workpiece surface is not bombarded with ions capable of damaging the surface (more than about 10 cm) and sufficiently close to the workpiece that reactive plasma products exist in the flow (within about 30 cm).
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: November 7, 1995
    Assignee: AT&T IPM Corp.
    Inventors: Eray S. Aydil, Konstantinos P. Giapis, Richard A. Gottscho