Abstract: A semiconductor device (10, 40) is formed to have a well (19) in a substrate (11). The well and the substrate have the same doping type, for example both P-type or both N-type. Low resistance contact regions (26, 27) of a second conductivity type are formed to at least abut the well. A drain (17) is formed within one low resistance contact region. A source (12) is formed in the substrate and laterally displaced from the other low resistance contact region. A buried layer (21, 22, 23) is formed laterally across the well.

Abstract: A voltage detection device (10, 30) utilizes grounded gate J-FET transistors (16,17,18) to detect desired input voltage values. The grounded gate J-FET transistors (16,17,18) function in different modes as the input voltage varies to facilitate detecting the desired input voltage values.

Abstract: Individual pressure sensitive devices 183 fabricated on a wafer 182 are individually over pressure tested by hermetically securing the wafer 182 between a first plate 105 having individual chambers 135 coupled to an inlet 125 thereon, and second plate 110 having individual chambers coupled to an outlet 130 thereon. A predetermined vacuum generated by a compressor 115 coupled to the first plate 105 is applied to the individual pressure sensitive devices 183 on the wafer 182 for a predetermined duration. Subsequently, a predetermined vacuum generated by a vacuum generator 120 coupled to the outlet 130 is applied to the individual pressure sensitive devices 183 on the wafer 182 to remove disintegrated fragments of the individual pressure sensitive devices 183 on the wafer that fail the over pressure test to minimise contamination.