Abstract: A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

Abstract: A doubly balanced transceiver system having a transmit terminal (TX), a receive terminal (RX), and an an antenna terminal (ANTENNA), 180° hybrids (201, 240), 90° hybrids (204, 304, 235 and 335), a power amplifier (230, 330) and a RX/TX switch (220) for disabling the power amplifier so that signals received at the transmitter are reflected to the receive terminal (RX). The 180° hybrids (201, 240) preferably split and re-combine signals into parallel paths. A loopback test mode is preferably provided by use of an antenna isolation switch (302) to enable a power detect terminal (POWER_DETECT). This eliminates pricey and problematic GaAs switches, and allows the use of low cost silicon for the power amplifier. The doubly balance architecture also has the advantage of eliminating common-mode noise, and reflection problems with the PA gain stages. Additionally, greater power can be extracted from the power amplifier. Further the arrangement has less insertion loss compared to a GaAs switch.

Abstract: A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

Abstract: Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

Abstract: A memory (110) uses memory cells not intended for user programming referred to as ‘dummy’ cells (202, 206). When selected, the dummy cells provide a current that establishes a reference voltage substantially equal to one-half of voltage created in a bit line by a cell programmed to a one and a cell programed to a zero. The reference voltage is sensed and compared with a bit line voltage created when a memory cell is read. By time multiplexing either one dummy cell programmed to a logic one or two dummy cells per bit line programmed respectively to logic one and logic zero, the desired reference voltage is accurately created. Memories such as MRAM and Flash that may be is difficult to accurately sense due to cell processing variations are enhanced by the timed selective use of one or more dummy cells.

Abstract: A machining apparatus (10) comprises a material removing tool (12) movably mounted for removing material from a workpiece (14); means for illuminating (42, 54) a sample area upon a tool surface (34) with excitation radiation; means for receiving (42, 54) sample light emitted from the sample area; a spectral analyzer (54) for performing a spectral analysis of the sample light received; and means for determining (60) the condition of the tool at the sample area from the spectral analysis of the sample light. The wear of the tool (12) is determined as such a condition. Operation parameters of the machining apparatus (10) are adjusted according to the determined wear. An example application is a wafer dicing tool.