Abstract: A method of using a computer system 20 to implement a graphical interface 10. The method displays a graph 160 of data from a database system 11, and permits a user to change the data by changing the appearance of the graph 160. The graph 160 is generated from a stored graphics engine 12, which contains rules for generating graphical objects comprising the graph and the objects' attributes. The graphical objects and attributes are matched to data delivered from the database system 11. If the user manipulates a graphical object, the graphical interface 10 associates the change to a new data value, and updates both the graph 160 and the data in the database system 11.

Abstract: A system for dynamically allocating memory to a file buffer cache manager and a virtual memory space manager is provided. The file buffer cache memory is time stamped at times of acquisition and access, and the acquired virtual memory space memory is time stamped at times of acquisition and access. If the file buffer cache manager or the virtual memory address manager requests memory, the time stamps of the memories acquired by the file buffer cache manager and the virtual memory space manager are compared. The piece of memory which has the earlier time stamp is preempted and allocated to the manager which has requested memory.

Abstract: An improved arbitration system is disclosed for arbitrating signals at a plurality of input nodes to output nodes where each input node can access any output node. The system includes a FIFO (first-in-first-out) input queue for each node and means for arbitrating the top of each queue for providing the arbitrated output to a given node and means when the top of the input queue has no request for a given node arbitrating the requests from the next to the top entry of the input queues and providing the data from the next to top entry associated with the arbitrated request to the given node.

Abstract: A system and method of determining the quality of a received facsimile signal is provided herein by measuring the received signal from a digital modem receiver 60. The end of a scan line is detected by looking for the special code of eleven logic 0s followed by a logic 1. The distance value between the position value of the received signal elements and the standard reference position is determined and if this distance exceeds a given threshold that is recorded and the percentage of those that exceed this threshold distance identifies the quality.

Abstract: A combiner/memory system interconnects a plurality of computer systems using for example the new HIPPI standard link. The combiner system includes it's own internal storage for rapid shared access to all connected computer systems. The combiner/memory system includes a smart switch for reading header information, arbitrating messsages and connecting computers to each other or to the internal shared storage. The system also includes a mechanism for synchronization of cooperating processes.

Abstract: The present invention includes processing circuitry (11) interfacing with a multi-process environment (10) for performing a method of determining an average batch size. A processor (12) receives input parameters corresponding to characteristics of the multi-process environment (10) from interfacing circuitry (18). These input parameters generate a first utilization factor which generates a first estimate of the average batch size during a first iteration step. A second utilization factor and in turn a second estimate of the average batch size are generated during a second iteration step.

Abstract: A technique and a mechanism accurately determines the correct prefetch line for loops with strides of 1, N, or a combination of stride values. Stride registers are used to assist in prefetching. Furthermore, stride register values can be used to specify "cacheability" of data on an object by object basis to prevent "cache flushing". The compiler uses a new instruction, "MOVE GPR TO STRIDE REGISTER", prior to a loop to insert the "calculated stride value(s)" into the stride register(s) associated with the index register(s) which will be incremented by that stride value. At the end of the loop, a second new instruction, "CLEAR STRIDE REGISTER SET", is used to place a value of zero in all of the stride registers to inhibit prefetching of data which would most likely not be used. A zero value in the stride registers inhibits prefetching. Non-zero values in the stride registers clearly mark the execution of a loop, which is where prefetching makes the most sense.

Abstract: A method and system for covertly determining and predicting air-to-air target data relative to a predetermined position passively senses the target (84) to produce a passive target data set. Next, the method and system transform (14) the passive target data set to produce a transformed passive data set. Then, the system compares (22) the transformed passive data set to a predicted data set (20) to generate a measurement error. By actively sensing (38 and 40) the target for a minimally detectable period (42) of time to produce an active target data set (28), the system applies constraints (28) and therefrom computes penalties (26) that relate to the measurement error (22) to produce a system error. Then, in response to the system error (24) the method and system compute the direction (30) and magnitude (32) for a perturbation or a response (44) to the predicted target data (18).

Abstract: System (100) receives a speech signal at an input (102) which is measured and transformed by speech feature measuring device (104). The output feature vector from speech feature measuring device (104) is then compared to a reference model in a statistical classification manner. Acoustic similarity measuring device (106) performs statistical measurements while temporal speech model constraints block (108) imposes transitional probabilities to the probability measurements generated by measuring device (106). Acoustic similarity measuring device (106) performs a weighted analysis of the error vector defined between the speech feature vector and reference vector utilized during the analysis.

Abstract: Dynamic address translation structures and procedures are capable of multiple address translations for the same processor in a single cycle. According to one approach, a plurality of directory look aside tables (DLATs) are used to provide multiple address translation. The DLATs are accessed in parallel by separate virtual address generators. To avoid the problem of generating the same address multiple times for each of the DLATs, a generated address for one DLAT may be written to all the DLATs or, alternatively, if a miss occurs in one DLAT, a search is made of the other DLATs before the address is generated. In the former case, an address written to all the DLATs may overwrite an address that will be needed for a future translation by one of the other DLATs. This is avoided in the latter case, but translations in other DLATs are interrupted when a miss occurs in one of the DLATs. This, in turn, may be avoided by employing "shadow" DLATs which are copies of the DLATs.

Abstract: A method and system are provided for time aligning speech. Speech data is input representing speech signals from a speaker. An orthographic transcription is input including a plurality of words transcribed from the speech signals. A sentence model is generated indicating a selected order of the words in response to the orthographic transcription. In response to the orthographic transcription, word models are generated associated with respective ones of the words. The orthographic transcription is aligned with the speech data in response to the sentence model, to the word models and to the speech data.

Abstract: A method for evaluating application software used with a computer system having a graphic user interface. The method is implemented as a computer program that runs simultaneously with the application software. The program continually checks a system-provided event record to determine if a user-initiated event has occurred. If so, the program relates the event to an on-screen object of the graphic user interface and to the time at which it occurred. Events and objects and their attributes are associated with identifiers so that the invention can be programmed to select only certain event data. The program outputs an event capture log, which may be used for subsequent analysis.

Abstract: A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.

Abstract: A local area network system is provided in which a plurality of communications nodes (14 and 16) are operable to transmit and receive information across a plurality of communications links (10 and 12). A plurality of redundant adapters (18 and 20) are coupled between the communications links (10 and 12) and the communications nodes (14 and 16), such that the communications nodes (14 and 16) are capable of transmitting and receiving information across each of the communications links (10 and 12).

Abstract: A controller (210) for controlling a plurality of sequential tools (220.sub.1, 220.sub.2, . . . , 220.sub.n), such as dbx debuggers (dbx tools), operating in a parallel computing system. The controller executes each of these sequential tools on an individual node (245.sub.1, 245.sub.2, . . . , 245.sub.n) of a parallel computing system (100). The controller associates each tool with a particular process (230.sub.1, 230.sub.2, . . . , 230.sub.n) of a user program executing on a particular node. Typically, each tool accumulates specific performance characteristics of its associated process as data and transfers the data to the controller for ultimate display to a programmer. In particular, the controller in combination with various dbx tools operating on various nodes in the parallel computing environment produces a parallel program debugger (pdbx). As pdbx, the controller sends commands to particular nodes to control the operation of each dbx tool executing on that particular node.

Abstract: A method and apparatus are provided for allocating tolerances. A total tolerance is specified (218) to be allocated among a plurality of variable tolerances each having an associated assembly feature. For each associated assembly feature, an associated first tolerance point is defined (202) at which a further decrease in a stringency of the variable tolerance fails to significantly decrease a cost of achieving the variable tolerance. For each associated assembly feature, an associated second tolerance point is defined (202) at which a further increase in the stringency begins to substantially increase the cost of achieving the variable tolerance. For each associated assembly feature, an associated third tolerance point is defined (202) at which a further increase in the stringency is not substantially achievable.

Abstract: A high density computer interconnection assembly is provided by a plurality of flat packages slidably mounted along a rack in a frame in one given plane. The packages include edge connected processors and switch modules with associated power supply. One or two interconnection wiring circuit boards extend perpendicular to the one given plane and adjacent and along the edge of the edge connected modules to couple thereto whereby the interconnection circuit board couples said switch modules to said processor modules along one broad surface of said interconnection circuit board. Memory cards are coupled to the opposite broad surface of the interconnection circuit board.

Abstract: Computer elements in a massively parallel computer system are interconnected in such a way that the number of connections per element can be balanced against the network diameter or worst case path length. This is done by creating a topology that maintains topological properties of hypercubes yet improves flexibility by enumerating the nodes of the network in number systems whose base can be varied. Topologies are generated in which nodes are not always connected when their addresses differ in a single digit. A new variable d is introduced, the purpose of which is to control the overall density of the network by controlling the number of intermediate arc connections within the rings of the network.

Abstract: A method of processing a signal having characteristics and received from a telephone line is presented. The method includes defining a frame by measuring a plurality of samples from the signal over a predetermined period. Additionally, linear prediction coding coefficients of a selected group from the plurality of samples are determined. Further, the variance of the linear prediction coding coefficients are determined and the variances compared to a reference variance. A heuristic rule is applied to a selected characteristic of the signal to determine if the signal comprises a voice signal.

Abstract: An improved differential cascode current push-pull driver is provided by controlling the up level by clamping the collector node with respect to output signal reference VR to less than VCC. The collector resistors are made smaller so there is smaller signal swing and faster operation.