Patents Represented by Attorney, Agent or Law Firm Robert Lannucci
  • Patent number: 6294798
    Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: September 25, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Raffaele Zambrano