Abstract: A switched capacitor comparator having two or more stages of differential input operational amplifiers utilizing sequentially switched feedback portions and feedback capacitors is provided. The use of feedback capacitors in a sequentially switched comparator provides accurate gain and stability. To further reduce offset voltage errors, a solid state transmission gate having a low "on" resistance is disclosed. A transmission gate having capacitors for partially compensating parasitic capacitance effects, a P-channel device and an N-channel device with a switched tub or substrate is provided to compensate parasitic capacitance effects. When the transmission gate is conducting, the tub or substrate of the N-channel device is switched from one of its current electrodes to a reference potential such as ground. Before the transmission gate is opened electrically, a settling time is provided to allow charge which is coupled from parasitic capacitance to settle.

Abstract: A digital to analog converter which provides positive and negative analog output signals in response to a digital input number is disclosed. The input number has n bits including a sign bit and n-1 magnitude bits, where n is an integer. An input receives the n-1 magnitude bits and is coupled to switches for selectively coupling a predetermined reference voltage to a capacitance portion comprising a rank ordered plurality of capacitors. First and second charges related to first and second portions of said n-1 magnitude bits, respectively, are sequentially integrated with respect to time by an integrator which is selectively coupled to the capacitance portion to provide an analog output signal. A buffer output amplifier selectively samples and holds the analog output signal.

Abstract: An amplifier circuit minimizes output voltage transients during powering up of the circuit. First and second bias current source portions are coupled to an input portion for receiving an input voltage. An amplifier portion is coupled to the input portion. The first bias current source portion provides a constant minimal current to the input portion which maintains the circuit bias voltage to the amplifier portion at near quiescent operating conditions. The second bias current source portion is switched to the input portion in response to a power control signal and provides bias current to the input portion necessary for circuit operation.

Abstract: A single input oscillator circuit which provides an oscillating output signal in response to the presence of an input signal is provided. A differential comparator stage having a predetermined trip point established by a reference voltage is connected between the input terminal and a set-reset latch circuit. A gain stage has an input connected to the input termial, and variable bias is derived from both the differential stage and a set-reset latch circuit for providing the output signal in response to the voltage level of the input signal. A discharge portion is connected to the input terminal to periodically couple the input terminal to a voltage potential node in response to the latch circuit.

Abstract: A gate array which has power bus routing for increasing current availability to a plurality of transistor cells is provided. The gate array also has separate power busses for input/internal logic and output circuits. The gate array comprises n columns of transistor cells with two power busses extending substantially along each column to power the cells. Input/internal logic power busses and separate output power busses extend around the perimeter of the columns of transistor cells. At least one power strip for increasing current availability to the transistor cells is routed across the transistor cells substantially perpendicular to the n columns and is connected to both the power busses of each column and to the input/internal logic power busses.

Abstract: An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

Abstract: A bias current reference circuit is disclosed having a first diode-connected bipolar device connected in series with an MOS device to develop a reference voltage which is proportional to a bias current. The reference voltage is used by an MOS device connected in series with a resistor which is connected in series with a second diode-connected bipolar device to develop a reference current which is proportional to the difference in the base to emitter voltages of the two bipolar devices. The reference current is used by a diode-connected MOS device to develop a bias voltage which is proportional to the reference current. The bias voltage in turn is used by another MOS device to develop the bias current in proportion to the bias voltage. The bias voltage is also used by other MOS devices to provide similar bias currents. In the disclosed embodiment, such a bias current can be used by a diode-connected CMOS device to develop a complementary bias voltage.

Abstract: A low leakage CMOS analog switch circuit comprising conventional MOS switches having transistors of high threshold voltages coupled to an interface circuit comprising transistors of low threshold voltages is provided. The N-channel threshold voltage of transistors in the switches is adjusted upward and the P-channel threshold voltage of transistors in the interface circuit is adjusted downward through the use of a single mask in one process step.

Abstract: A hysteresis circuit is added to a differential comparator to provide a predetermined bias current from one of two input transistors connected in a differential configuration. A current mirror structure is used to accurately determine the amount of current which is shunted when the output of the comparator is in a predetermined state.

Abstract: A CMOS operational amplifier includes a biasing scheme for supplying current to a differential stage. A push-pull output stage includes a current sinking transistor which is coupled to a first output of the differential stage. A current mirror is coupled between a second output of the differential stage and the gate electrode of a current sourcing device in the output stage.

Abstract: A temperature stable bandgap voltage reference source utilizing two substrate bipolar transistors biased at different emitter current densities is provided. Switched capacitors are used to input the V.sub.be and the .DELTA.V.sub.be of the transistors (NTC and PTC voltages, respectively) into an amplifier to provide a reference voltage proportional to the weighted sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors renders the reference voltage substantially independent of temperature. In a modified form of the reference, the reference amplifier is implemented by an auto-zeroed operational amplifier which uses switched capacitor techniques and an integrated capacitor to achieve the auto-zeroing function.

Abstract: An operational amplifier capable of selectively performing a variety of circuit functions is provided. A single operational amplifier utilizes switched capacitors for sampling and holding an input signal, for establishing a low frequency pole, for applying the sample to an output capacitance to charge the capacitance and for comparing the input signal with a reference. The multi-function circuit provides a large savings in circuit area and permits versatility of circuit applications. One embodiment of the invention is to utilize a companding DAC having a capacitor array which may be used as the output capacitance of the operational amplifier circuit. The DAC provided utilizes an R ladder DAC coupled directly to a C DAC and has a switching structure that is simpler than comparable prior art circuits. The DAC is asynchronous and has programmable A-and Mu-255 law PCM conversion capability.