Abstract: An apparatus receives a series of locations containing a row address and a column address of a fault detected within an array. A row replacement priority circuit within the apparatus logs the row address of the first fault detected, and thereafter marks a column of any subsequent faults detected in rows other than the row of the first detected fault. Concurrently, a column replacement priority circuit within the apparatus logs the column address of the first fault detected, and thereafter marks a row of any subsequent faults detected in columns other than the column of the first detected fault.
Type:
Grant
Filed:
May 20, 1999
Date of Patent:
December 4, 2001
Assignee:
International Business Machines Corporation