Abstract: An embodiment of the present invention is a switching power supply that includes a power switching device and a control circuit to control the power switching device. Under normal operational conditions the power required by the power switching device is provided by an auxiliary secondary winding of the transformer of the power supply. When the temperature sensitive device gets into an unallowed operational condition this is no longer possible and as a consequence the device is disabled for a period of time which is determined by the amount of overheating of the device.

Abstract: The present invention relates to multi-bit exclusive-or (XOR) gates (60), including those where N parallel input bits (36, 38) are XORed with one data input bit (52). A modular approach is made using only one basic cell (30) for various implementations with different propagation delays. An N-bit XOR comprises basic cells (30) of adjacent first and second XOR gates (32, 34). Each first XOR gate (32) processes as input two of said N primary input bits (36, 38) and each second XOR gate (34) processes as input bits output bits of first or second XOR gates (32, 34) or the input data bit (52). This structure makes it possible to create an array of identical basic cells which is very suitable for VLSI implementation. There are few lines of connections between the different cells in the cell array which leads to substantial reduction in propagation delay without adding substantial wiring or layout complexity.

Abstract: A circuit (100) has a pull-up transistor (110), a pull-down transistor (120), an input driver (200). The pull transistors (110, 120) pull an output line (102) to first or second reference lines (101, 103). The output line (102) can assume a potential higher than the potential at the first reference line (101). The circuit (100) further comprises protection transistors (150, 160, 170, 180). The protection transistors compare the potential at the output line (102) with the potential at the first reference line (101). The protection transistors keep a substrate line (106) of the pull-up transistor (110) at the potential of the output line (102) or at the potential of the first reference line (101), whichever is higher.

Abstract: An apparatus and method is provided with hysteresis for switching a load according to an input signal. There is a transfer gate for transferring a first signal to a second signal. A controller receives the first signal and the second signal and provides a control signal for the transfer gate. The control signal enables the transfer gate if the first signal reaches a first magnitude and disables the transfer gate if the first signal reaches a second magnitude. The control signal is obtained from a voltage divider across the first signal. A portion of the voltage divider is shorted out by a switch activated by a second signal. Thus, the control signal depends on the second signal. The apparatus is entirely powered by the second signal.

Abstract: An encoding system (400) receives samples and coefficients from a bus (422). The system comprises a plurality of parallel operating memory devices (430-k), registers (435-k), computing units (440-k), and accumulator units (460-k). The system (400) further comprises a parallel-to-serial buffer (470) coupled to the accumulator units (440-k) and a pair generator (480) for providing amplitude/index pairs. The system (400) performs encoding steps such as transforming, quantizing, zigzagging, rate controlling, and run-length coding. Transforming is explained for the example of a Forward Discrete Cosine Transformation (FDCT). According to a method (500) of the present invention, zigzagging (510) occurs prior to transforming (570) and performed only once when transformation coefficients are provided to the memory devices (430-k) in a zigzag arrangement. Quantizing occurs prior to transforming by pre-calculating the coefficients with quantizers.

Abstract: The rise time of a voltage Vo presented to a load, based on an input voltage Vi provided via an RC filter coupled to the load for removing higher frequency noise on Vo, is substantially reduced by providing a sensor circuit with differential inputs Vi, Vo. The sensor circuit drives a charger circuit coupled to a DC potential and the load so that rapid charging of C to Vo does not depend on R. As Vo approaches Vi, the sensor circuit deactivates the charger circuit to stop further charging and a latch coupled to the sensor circuit shuts off the sensor circuit to reduce power consumption while (Vo.about.Vi)>0. A current mirror buffer is desirably included between the sensor output and the latch for level shifting.

Abstract: A switched mode power supply has a transformer and a power switch to switch a primary current for operation in a critical conduction mode. The switched mode power supply has a controller which switches off a primary current when a peak current is reached. The primary current is switched on again when a zero current condition in the secondary is detected the first time after the primary current has been switched off and a minimum primary current off time has been reached.

Abstract: Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

Abstract: In a bandgap reference circuit (200), a base-emitter voltage V.sub.BE with a first temperature coefficient TC.sub.1 is added to a voltage difference .DELTA.V with a second, opposite temperature coefficient TC.sub.2 by two resistors (210,220). The bandgap reference circuit (200) comprises current sources (271-276) and bipolar transistors Q(1) to Q(K) (281-286) of pnp-type and npn-type. Current densities in Q(1) to Q(6) are distributed so that some base-emitter voltages V.sub.BEk in Q(1) to Q(6) are different. The bases and emitters of Q(1) to Q(6) are serially coupled so that pn-junctions are arranged in a alternative directions, thus adding only the differences of V.sub.BEk but not adding their absolute values. This feature makes the circuit (200) applicable in a low voltage environment. The ratio between the two resistors (210,220) can have a value which minimizes noise voltages V.sub.N so that external filtering capacitors are not required.

Abstract: The amplifier (200) includes an input stage (220) coupled to two output transistors (281, 282) having a common terminal at the output terminal (206) of the amplifier. Class AB operation of the output transistors (281, 282) is possible at a comparatively low supply voltage. In order to obtain such operation, measurement transistors (271, 272) are coupled to the same control input (283, 284) as the output transistors (281, 282). These measurement transistors (271, 272) are serially coupled to a current mirror (260). The quiescent current of the output transistors (281, 282) is measured and used to produce a feedback signal which is superimposed to the control signals.

Abstract: The intermediate frequency (IF) amplifier (10) of the invention comprises a differential stage (40) having transistors (41, 42) serially coupled to inductive loads (31, 32). There is only one point at common sources (node 45) which is sensitive to spikes. A feedback stage (60) extracts a common mode spike component at spike frequency (f.sub.S) from the output and returns a feedback signal to the sensitive point (node 45). Comparing to traditional differential amplifiers, the common mode rejection at resonance frequencies (f.sub.R) can be 30 times higher. This makes the amplifier (10) spike insensitive and suitable for the integration into mixed analog-digital chips, such as DSP chips, where the analog portions operate in the same frequency range as the digital portions.

Abstract: An analog-to-digital converter is introduced which operates as an oversampled delta-sigma converter. The converter is implemented fully differentially, having doubled integrator capacitors (130, 230), comparators (180, 280), and feedback units (160, 260). In order to reduce the influence of parasitic capacities, the feedback units (160, 260) comprise cascoded switches (171-179). Internal auxiliary signals for controlling the feedback units (160, 260) return to zero at clock frequency. The converter can be used in an integrated signal processing circuit having analog and digital domains on one chip. The capacitors (130, 230) itself are implemented by MOS transistors with the same single poly process as the rest of the circuit. In a second embodiment of the invention, the analog-to-digital converter (500) comprises multiple comparators (580, 572, 573, 574), dynamic matching circuits (801, 802). The comparators (572, 573, 574) can received dithered input signals.

Abstract: A linear voltage-to-current converter (VIC) 100 for converting a differential input voltage V.sub.D into a differential output current ID is provided. The VIC (100) comprises a main stage (20) and a correction stage (30) having two FET each. Every stage is fed by a separate current source (150, 160). In two nodes (174, 172) the output currents of the stages are added. The scale factors k.sub.1 and k.sub.3 of the FET are coordinated so that distortions are reduced.

Abstract: A high frequency monolithic amplifier (100) is provided which can be used, for example, in the PLL prescaler of cellular radio systems. The amplifier (100) amplifies single-ended signals having a frequency in the GHz area. It includes a feedback unit (160) which uses parasitic capacitors. The feedback depends on the frequency and is positive for high frequencies and negative for low frequencies. A high gain can be obtained for high frequencies. A comparative low gain a low frequencies prevents the propagation of noise. The amplifier (100) of the present invention can be cascaded to an, for example, 3 stage amplifier arrangement (300).

Abstract: In a clock generator (100), an oscillator (30) supplies an oscillator signal (38) to a first trigger (10) and to a second trigger (20). The triggers change the oscillator signal (38) to a first and a second trigger signal (18, 28). The second trigger (20) has a larger hysteresis range than the first trigger (10), so that the first trigger signal (18) starts toggling before the second trigger signal (28) starts toggling. A detector (40) determines that the second trigger signal (28) toggles at least three times, that means that the oscillator signal (38) goes over the larger hysteresis range in two directions. The detector (40) provides a result to a control circuit (50) which derives a clock signal (98) from the first trigger signal (18).

Abstract: A differential-to-single-ended converter comprising a resistor network (205) and an operational amplifier is introduced. In comparison to prior art converters, a resistor (250) placed between the non-inverting input (264) of the operational amplifier (260) and the negative input terminal (202) of the converter (200). The common mode voltage (V.sub.nii ') at the non-inverting input (264) does not depend on the differential input voltage (V.sub.in.sup.#) of the converter (200) and has low fluctuations. This allows the use of an operational amplifier (260) with low CMRR and makes the converter (200) suitable for low voltage applications.

Abstract: A digital-to-analog (D/A) converter (400) receives a N bit digital signal S.sub.N by a signal divider (440) which divides it into digital group signals S.sub.Nk. In converter blocks (401.sub.k), these digital group signals S.sub.Nk are then separately converted into analog group signals S.sub.Gk. In a summation circuit (460) these analog group signals S.sub.Gk are combined to the analog signal S.sub.A. The converter blocks (401.sub.k) can comprise banks (430.sub.k) with, e.g., current sources whose currents I.sub.i are combined into the analog group signal S.sub.Gk selectively according to the digital group signal S.sub.Nk. The converter blocks (401.sub.k) can include circuits to equalize component variations, such as dynamic matching circuits (480.sub.k). The converter blocks (401.sub.k) can be configured according to the significance of the digital group signals S.sub.Nk and the hardware can be optimized.

Abstract: The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.

Abstract: In a method for operating an electric motor especially a permanent magnet motor, the voltage applied to the windings of the stator of the motor are commuted electronically. The timing of the commutation events is determined by sensing and low pass filtering the differential voltages between the windings and detecting the zero crossings of the filtered differential voltages. At the time the zero crossings take place or within a short time afterwards the commutation events take place.

Abstract: A system rapidly dynamic values (B) on a bus (12) to a programmable but thereafter fixed reference value (C). The system includes first leads (33) coupled to a comparison means (35), second leads (13) coupled to the bus (12) and third leads (34, 36) coupled to sources of potential (GND, VCC) related to logical HIGH and LOW of the fixed reference value (C). The leads (33, 13, 34, 36) are coupled in one or more programmable connection cell (32). Connections (471) or disconnections (461) are made between the leads (33, 13, 34, 36) so that the dynamic values (B) and the appropriate logical HIGH and logical LOW values are presented to the correct inputs of the comparison means (35). The programmable connections cells (32) invert the reference value (C) to (C) for coupling to the comparator (35). The system replaces a level of conventional decode logic (16) by the programmable interconnections (47), thereby reducing delay time, using fewer devices and occupying less circuit area.