Abstract: An apparatus comprising a synchronous circuit configured to (i) shift a JTAG instruction signal in response to a first control signal, (ii) decode the JTAG instruction signal while the JTAG instruction signal is shifted and (iii) latch the decoded JTAG instruction signal in response to a second control signal.

Abstract: An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals.

Abstract: An integrated circuit comprising a memory and a logic circuit. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The logic circuit may be configured to generate a predetermined number of the internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) one or more control signals. The generation of the predetermined number of internal address signals may be non-interruptible.

Abstract: A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.

Abstract: A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.

Abstract: An apparatus comprising one or more output circuits each configured to configure a pad as either an input/output pad, a power pad, or a ground pad in response to a plurality of configuration inputs.

Abstract: An apparatus comprising one or more configuration blocks. The configuration blocks (i) may comprise a number of configuration elements and (ii) may be configured to initiate reading or writing of the configuration elements in response to a control input.

Abstract: An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.

Abstract: An apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.

Abstract: A programmable logic device comprising a plurality of configuration blocks that may be configured to store configuration information for configuring the programmable logic device. The configuration blocks may be simultaneously programmed.

Abstract: A logic section of a programmable logic device comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output in response to a first input, a second input and a third input. The second circuit may be configured to generate a second output and a third output in response to a fourth input and a fifth input. The second output may be coupled to the second input and the first output may be coupled to the fifth input.

Abstract: An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate one or more first parallel data signals in response to a first serial data stream and a first control signal and (ii) generate a second serial data stream in response to one or more second parallel data signals and a second control signal. The second circuit may be configured to write the one or more first parallel data signals to and read the one or more second parallel data signals from an array of storage elements in response to one or more control signals.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to drive a first bus in response to a first control signal. The second circuit may be configured to control a voltage of the first bus in response to the first control signal.

Abstract: A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (i) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.

Abstract: A circuit and method comprising a memory array and a plurality of address circuits. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.

Abstract: A circuit is presented comprising a first device and a second device. The first device may be configured to operate at a first supply voltage and may be configured to generate a pull-up signal in response to an input signal. The second device may be configured to operate at a second supply voltage. The second supply voltage may be lower than the first supply voltage. The second device may be configured to generate an output in response to (i) the input signal and (ii) the pull-up signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to generate a sleep signal in response to (i) said control signal and (ii) a clock signal.

Abstract: A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (ii) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.