Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: Polishing rate selectivity is increased by providing a polyelectrolyte in the polishing slurry. The polishing selectivity of silicon oxide to silicon nitride is enhanced by using an anionic polyelectrolyte. The polishing selectivity of metals to silicon oxide, silicon nitride and/or silicon oxynitride is increased by using a cationic polyelectrolyte.

Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line. More particularly, the present invention is directed to a thin film transistor comprising a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk running from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.

Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including an ultra-thin top Si-containing layer and at least one patterned buried semi-insulating or insulating region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form a first implant region of the first ions in the Si-containing substrate. Following the implantation of first ions, a first annealing step is performed which forms a buried semi-insulating or insulating region within the Si-containing substrate. Next, second ions that are insoluble in the semi-insulating or insulating region are selectively implanted into portions of the buried semi-insulating or insulating region. After the selective implant step, a second annealing step is performed which recrystallizes the buried semi-insulating or insulating region that includes second ions to the same crystal structure as the original Si-containing substrate.

Abstract: The present invention embodies high-accuracy white point adjustment with a simple circuit configuration according to an efficient algorithm in a display system for full digital processing. More particularly, the present invention is directed to a digital video interface 13 for inputting a digital video signal outputted from a host system and a liquid-crystal display monitor 11 for applying color conversion to the digital video signal inputted by the digital video interface 13 without using a look-up table, in which an adjusted-value input logic for inputting adjusted values at predetermined points to achromatic colors between maximum- and minimum-gray-scale achromatic colors and a controller LSI 22 for computing a digital video signal inputted by the digital video interface 13 so as to converge chromaticity coordinates for achromatic colors and outputting a computed digital value in a pipeline manner are used.

Abstract: A method is described for repairing failure points, regions or locations in an electronic device to have a perfect function when a semiconductor device including an LCD or other electronic device has defects. Described is a method of transferring a single or multi-layer thin film piece into a recess with the physical properties of the thin film piece unchanged. An electronic device is described incorporating a substrate; and a plurality of thin films laminated on the substrate and part of the thin films are formed on a predetermined circuit pattern, wherein a transfer film for repairing a defect is fitted into a recess where the low layers of the thin films are exposed by removing part of a single or multi-layer thin films covering a defective portion included on the thin films and its surrounding portion.

Abstract: The object of the present invention is to reduce the number of inputs to LCD driver chips, and to suppress the occurrence of variances between the chips. A ten bit wide binary counter 202 is self activated in synchronization with a system clock. Each of multiple five-step shift registers 200 having ten bit widths stores gamma compensation data received from a PC. Each of multiple comparators 204 compares a binary counter value (X) with a value (Y) stored in a ten bit wide five-step shift register 200, and converts the gamma compensation data into a pulse width. The output of each comparator 204 is latched by each of multiple D-FFs 206 in synchronization with the system clock, and each of multiple time/voltage converters 208 passes the output of a D-FF 206 through an LPF and generates a reference gamma compensation voltage.

Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leakage current from another signal line. A thin film transistor comprises a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer 27 formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk leakage current flowing from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.

Abstract: A liquid crystal (LC) lightvalve comprising a twisted nematic LC layer whose molecules are aligned with pixel edges at the mirror backplane, thereby providing improved contrast and efficiency, and reduced visibility of post spacers in black state. The present invention is directed to an LC structure wherein the backplane is rubbed in a direction rectilinear with pixel edges. The LC layer is given the same twist rotation and birefringence as in the conventional TN lightvalve. Polarization control is maintained by illuminating the lightvalve with light whose polarization is rotated by the twist angle relative to the x,y, pixel axes, and by collecting the orthogonally polarized component of the reflected light. The lightvalve top glass is thus rubbed in a direction which is rotated by the twist angle from the horizontal or vertical direction at which the backplane is rubbed.

Abstract: A liquid crystal device (and method for forming the LCD) includes a first transparent substrate having a first surface and a second surface, and a second transparent substrate having a first surface and a second surface. The first transparent substrate and the second transparent substrate are arranged such that the first surface of the first transparent substrate faces the first surface of the second transparent substrate, and a liquid crystal material is enclosed between the first surface of the first transparent substrate and the first surface of the second transparent substrate. A pixel array, in which a plurality of pixel regions are arranged in row and column directions and data signals are applied to the pixel regions through data lines, is formed on the first surface of the first transparent substrate and the first surface of the second transparent substrate.

Abstract: A liquid crystal display panel (and a method for manufacturing the liquid crystal display panel) includes a gate line and a signal line intersecting the gate line at an intersection portion where the gate line and the signal line intersect each other. The gate line includes at least two conductive portions and at least one opening portion on the intersection portion.

Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, cyclic siloxanes and organic molecules containing ring structures, for instance, tetramethylcycloterasiloxane and cyclopentene oxide.

Abstract: The present invention is directed to a thin film transistor (and related multilayer structures) that includes: source and drain electrodes 14 and 15 disposed at a specified interval above an insulating substrate 11 and formed by printing-and-plating; an a-Si-film 16 disposed for the source and drain electrodes 14 and 15; a gate insulating film 17 laminated on the a-Si film 16; and a gate electrode 18 laminated on the gate insulating film 17 and formed by printing-and-plating. The a-Si film 16 and the gate insulating film 17 have an offset region 20 that uniformly extends beyond the dimensions of the gate electrode 18.

Abstract: Disclosed are an inspection method for a disconnection of a storage capacitor line and an inspection device for the same in an inspection of an array substrate used in a liquid crystal display apparatus. An inspection method for an array substrate is constituted, in which a quantity of charges stored in the storage capacitor becomes C (Vd1−Vcs1) by supplying simultaneously a pulse signal Vd and a pulse signal Vcs to the storage capacitor from a signal line and a Cs line on a TFT array substrate, and an influence of the disconnection of the Cs line is taken into consideration when the above-described quantity of charges is detected in a reading circuit. Note that the above-described inspection is performed not for all the storage capacitors, but for one storage capacitor in each Cs line. Thus, the inspection for all the Cs lines in liquid crystal panels from 14 inch diagonal to 18 inch diagonal is terminated in about 1 to 2 seconds.

Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: A method to selectively cap a cooper BEOL terminal pad with a Cu/Sn/Au alloy. The method includes providing one or more Cu BEOL terminal pads and coating the pads with a Sn coating followed by coating the Sn with a Au coating. The coated pads are then annealed to form the Cu/Sn/Au capping alloy.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

Abstract: In an integrated circuit structure, such as in an MCM or in an SCM, a particulate thermally conductive conformable material, such as a thermal paste, is applied between a heat-generating chip and a cooling plate. Modification of the microstructure of at least one of the two nominally parallel surfaces which are in contact with the material is provided in a discrete pattern of sloped recesses. The largest particles in the material preferentially migrate downward into the recesses. The average thickness of the conductive paste is reduced to below the diameter of the largest particles dispersed in the material, providing improved cooling.

Abstract: A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer.