Abstract: A circuit is designed with a register circuit (70) arranged to store a control word. A voltage-controlled oscillator (73) is coupled to receive the control word (72) and produce a clock signal (76) having a current frequency corresponding to the control word. A phase detector circuit (53) is coupled to receive a reference signal (52) and the clock signal. The clock signal has one of a phase lead and a phase lag with respect to the reference signal. The phase detector circuit produces a phase signal (58) having a first state in response to the phase lead and having a second state in response to the phase lag. An estimate circuit (69) is coupled to the register circuit and the phase detector circuit. The estimate circuit produces a next control word (71) corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.

Abstract: A protection circuit is designed with an external terminal (300), a reference terminal (126) and a substrate (342). A semiconductor body (338) is formed by an isolation region (332, 340) formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal (354) connected to a common control terminal (321) and a respective current path connected between the external terminal and the reference terminal. A capacitor (314) is connected between the semiconductor body and the external terminal. A resistor (318) is connected between the semiconductor body and the reference terminal.

Abstract: A circuit is designed with a detector circuit (700) coupled between a supply voltage terminal (705) and a reference voltage terminal (755). The detector circuit produces a first control signal in response to a detected mode and produces a second control signal in response to another mode. A first circuit (205, 207) including a delay circuit receives the first control signal and a third control signal. The delay circuit produces a fourth control signal at an output terminal (215) in response to the first and third control signals. A second circuit (203) receives the second control signal and the third control signal. The second circuit produces the fourth control signal at the output terminal in response to the second and third control signals.

Abstract: A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signal (*CLK) in response to the second logic state. The second clock signal has a frequency at least twice a frequency of the first clock signal. An address counter (221) is coupled to receive one of the first and second clock signals. The address counter produces a sequence of address signals corresponding to the one of the first and second clock signals. An array of memory cells is arranged to produce a sequence of data bits corresponding to the sequence of address signals. A logic circuit (235, 239, 240) is coupled to receive the sequence of data bits. The logic circuit produces a logical combination of the sequence of data bits.

Abstract: A circuit for replacing an array element with a redundant element in a semiconductor device is designed with a programmable circuit (128) storing an internal address and coupled to receive a buffered address (120 and 122). The programmable circuit (128) produces first (130) and second (132) redundant addresses in response to the internal and buffered addresses (120 and 122). A first decoder circuit (140), produces a signal to enable the redundant element (142) in response to the first redundant address (130). A second decoder circuit (148) produces a signal to enable the array element (150) in response to the second redundant address (132).