Abstract: In a computer system, a system and methodology for dynamically allocating available physical memory to addressable memory space on an as needed basis, and to recover unused physical memory space when it is no longer needed. Physical memory is assigned to addressable memory space when that memory space is first written. When the system software determines it has no further need of a memory space, the physical memory is recovered and made available for reuse.

Abstract: A system including a CPU, memory, and compression controller hardware, and implementing a first directory structure included in a first memory wherein CPU generated real memory addresses are translated into one or more physical memory locations using the first directory structure, further includes a second directory cache structure having entries corresponding to directory entries included in the first directory structure. In a first embodiment, the second directory cache structure is implemented as part of compression controller hardware. In a second embodiment, a common directory and cache memory structure is provided for storing a subset of directory entries in the directory structure together with a subset of the memory contents.

Abstract: System and method for reducing data access latency for cache miss operations in a computer system implementing main memory compression in which the unit of compression is a memory segment. The method includes steps of providing common memory area in main memory for storing compressed and uncompressed data segments; accessing directory structure formed in the main memory having entries for locating both uncompressed data segments and compressed data segments for cache miss operations, each directory entry including index for locating data segments in the main memory and further indicating status of the data segment; and, checking a status indication of a data segment to be accessed for a cache miss operation, and processing either a compressed or uncompressed data segment from the common memory area according to the status.

Abstract: A system for accessing contents of the directory structure in a computing system having a CPU and implementing indirectly addressable main memory via a first directory structure included in the memory. In this system, CPU generated real memory addresses are translated to one or more physical memory locations using the directory structure. A second directory structure is provided in main memory that includes one or more entries with each entry formatted to provide addressability to a predetermined number of entries in the first directory structure. The second directory structure alternately may access all contents of main memory, and is adaptable as main memory capacity varies. The second directory structure may alternately be implemented as a hardware device which computes the addresses for accessing data in main memory.

Abstract: In a cache memory system, a mechanism enabling two logical cache lines to coexist within the same physical cache line, during line fill and replacement, thus minimizing the likelihood of stalling accesses to the cache while the line is being filled or replaced. A control mechanism governs access to the cache line and tracks which sub-cache line units contain old or new data, or are empty during the fill/replacement procedure. The control mechanism thus maintains a sub-cache line state for the purpose of permitting a processor to gain access to a portion of the cache line before it is completely filled or replaced.

Abstract: A method and structure for a system for maintaining coherence of cache lines in a shared memory multiplexor system comprises a system area network and a plurality of compute nodes connected to the system area network. Each of the computer nodes includes a local main memory, a local shared cache and a local coherence controller and computer nodes external to a given compute node include external shared caches and the coherence controller includes shadow directories, each corresponding to one of the external shared caches. Each of the shadow directories includes state information of the local main memory cached in the external shared caches. The shadow directories include only state information of the local main memory cached in the external shared caches.

Abstract: A highly-efficient system and methodology for organizing, storing and/or transmitting compressed data that achieves optimum compression throughput, enhances overall data compressibility, and reduces decompression latency.

Abstract: In a high-speed computer system using multiple compression and decompression engines, a method and apparatus for coding and parsing compressed data in the decompressor in order to avoid bottlenecks within the decompressor that prevent it from achieving optimum latency and throughput acceptable to the system processor.

Abstract: The present invention is directed to a mobile agent technique, and in particular to a method for moving/transmitting to a desired computer, an agent and a message that the agent issues. According to the present invention, a temporary storage area (a computer having a storage device) for a destination computer of a mobile agent and a message is provided. When a mobile agent or a message can not move directly to a destination computer, the mobile agent and the message are temporarily stored in the temporary storage area. At an appropriate time, the destination computer extracts from the temporary storage area the agent and the message addressed to it. Since the temporary storage area is provided, the movement of the agent and the transmission of the message are ensured. Also because the temporary storage device is provided, the destination computer can accept a mobile agent and a message in accordance with the situation and the condition of the destination computer.