Abstract: An MOS mesa transistor is comprised of a silicon island on an insulating substrate. The silicon island consists entirely of a source region, a drain region, and an I-shaped channel region which separates the source and drain regions. The island has a coating of an oxide of silicon thereon. A rectangular conductive gate is adjacent to the coating and above the channel region and the transverse extremities of the I-shaped channel region extend bilaterally and transversely from underneath the gate at each end thereof.

Abstract: A method for making a four-layer P+PNN+ or N+NPP+ diode, and the diode, wherein the impurity profile about the PN junction is optimally graded for TRAPATT operation throughout the span of the avalanche region by ion implantation of the impurities to a depth of 1000A in a semiconductor wafer and wherein these impurities are subsequently thermally diffused.

Abstract: An improved means for interconnecting a semiconductor array to a carrier wherein the array comprises a plurality of MESFET transistors each having a distinct gate pad and a distinct drain pad, the improvement comprising a bilaterally symmetric conductive member connecting a plurality of pads, for example gate pads, to a common bus bar located on the carrier and a bilaterally symmetric conductive member connecting a plurality of pads, for example drain pads, to another common bus bar located on the carrier, wherein a length for each conductive member determines and provides a value of inductance at the operating frequency of the array which is substantially the same from the bus bar to each connected pad.

Abstract: A method for insuring that the sidewall of a P+ PN+ layered junction mesa semiconductor structure is tapered smoothly from the P layer to the N+ layer of the structure upon formation thereof by immersion of a wafer comprised of the structure in an etchant of 3% HF and 97% HNO.sub.3, comprising the steps of placing an etch mask dot having a diameter slightly less than the greatest diameter required for the N+ layer above the P+ layer at a preselected site on the wafer, preselecting a specific ratio of etchant quantity to P silicon quantity, immersing the wafer in the preselected quantity of the etchant, and withdrawing the wafer from the etchant at the instant at which the silicon is removed from around the dot.

Abstract: A uniformly electrostatically charged recording element is toned uniformly with magnetic toner particles and exposed simultaneously with both an image exposure and a separate flood light while the recording element is disposed in a magnetic field. The flood light is directed toward the uniformly toned (photoconductive) surface of the recording element while the image exposure is directed preferably onto the opposite (light-transmitting substrate) surface of the recording element.

Abstract: A susceptor for heating a plurality of semiconductor wafers, as by rf induction, comprises a hollow truncated pyramid of conventional graphite. The walls of the pyramid are planar except for ledges extending from the outer surfaces of the walls for supporting the wafers. A heat shield of pyrolytic graphite is fixed to the inner surface of the walls, directly behind each of the supported wafers. The heat shield has an area substantially coextensive and in alignment with the area of the wafer. The heat shields are anisotropic and are disposed with their low heat conducting directions extending in directions transversely to the surfaces of the walls so that the portions of the walls sandwiched between the wafers and the heat shields get hotter than the remaining portions of the walls.

Abstract: A method of obtaining a distribution profile of electrically active ions, of one type conductivity, implanted into a semiconductor, of an opposite type conductivity, is carried out with the aid of an integral target of the semiconductor. The integral target is formed with a plurality of doped regions of different background impurity concentrations, respectively, therein. Each of the operations of annealing, angle-lapping, and staining the doped regions to determine P-N junction depths therein is carried out on all of the doped regions simultaneously. An enlarged photograph of the stained angle-lapped portions of the doped regions provides directly a histogram of the distribution profile.

Abstract: The breakdown voltage of a novel insulated gate field effect transistor (IGFET), comprising silicon on sapphire (SOS), is substantially doubled by a novel structure wherein a dielectric layer, formed over a channel region of the IGFET, also extends continuously over the surface of the sapphire on opposite sides of the channel region. A polysilicon gate electrode is disposed over the dielectric layer, the gate electrode extending beyond the channel region and being separated from the sapphire substrate by the dielectric layer. The novel method of making the IGFET comprises providing an island of epitaxially deposited doped silicon on the sapphire substrate, and dielectric layer extending continuously over both the island and over portions of the substrate on opposite sides of the island.

Abstract: A light shield for selectively shielding light-sensitive elements in a semiconductor device from incident light comprises an opaque layer of material which is substantially nonreflective to light such as, for example, blackened photoresist, blackened metal, or a plastic containing particles of black carbon.

Abstract: An improved method of defining a pattern in a layer of organic material includes depositing a relatively thin layer of silicon dioxide on the layer of organic material, applying to the silicon dioxide layer a film of primer solution comprising a silane derivative, and then forming a photoresist etch mask on the film. By utilizing an ultrasonic etch bath, a uniform and well-defined pattern is etched in the layer of organic material.

Abstract: An improved insulated gate field effect transistor is achieved by using a material such as silicon nitride as an ion implantation and oxidation mask overlying a channel region, forming source and drain regions or extensions thereof by implanting ions of a conductivity modifier into a semiconductor substrate, and subjecting the implanted ions to a drive-in diffusion whereby the conductivity modifier ions are redistributed. The ion implantation allows greater control over the amount of conductivity modifier implanted in the lightly doped source and drain regions, the more uniform distribution of conductivity modifier increases the source-drain breakdown voltage, while the use of the silicon nitride mask provides simultaneously for general alignment of the channel region with the effective gate length.

Abstract: An improved method of manufacturing a semi-conductor device having a lead bonded to a surface thereof, wherein the device is fabricated by removing a section of a substrate which surrounds a surface portion of the substrate comprising the surface to which the lead is bonded, includes bonding the lead to the surface portion of the substrate prior to removing the section.

Abstract: A semiconductor device having a pair of laterally spaced multiple-layer metal films, each located in a different vertically-spaced parallel plane on a body of a single crystalline semiconductor material and a channel between the spaced edges of the pair of metal films. The edges of the pair extend in cantilever fashion over the channel. First and second laterally spaced Schottky-barrier metal films are located in the channel and form gate contacts. The first metal film is located completely beneath the uppermost multiple-layer film. The second metal film is located substantially below an aperture formed between the pair of multiple-layer metal films. A contact pad for the first film is on the outside of the channel near one end thereof, and a contact pad for the second film is located near the other end. The Schottky-barrier films are typically less than 0.8 micrometers wide.