Abstract: A method and apparatus for distributing, generating, and redeeming discount coupons, rebate or gift certificates or the like tracks each coupon using a consumer ID number printed on the coupon. Coupons may be distributed electronically, for example, in the form of a diskette or CD-ROM software. Software on the diskette or CD-ROM may prompt a consumer to call a 1-800 number for a validation number or code. During the phone call, telemarketing personnel may request consumer demographic and or identification information which may be entered into a centralized database. Once the software is validated, a consumer may print out selected coupons displayed on a Graphical User Interface (GUI). Each coupon may be printed only a limited number of times. Each coupon may be imprinted with a consumer ID number, preferably in the form of a bar code. Once redeemed, consumer ID information and coupon information may be retrieved from coupons forwarded to a coupon clearing house.

Abstract: A graphics controller circuit for upscaling source video image to generate an upscaled video image. The graphics controller circuit generates additional pixel data for the upscaled video image by interpolating source video pixel data of a one scan line and an another scan line. However, when source video pixel data of the another scan line may not be available for interpolation, the graphics controller circuit generates additional pixel data from source video pixel data of only the one scan line. Source video pixel data of the another scan line may not be available, for example, as a bus that transfers the pixel data may not have sufficient amount of bandwidth.

Abstract: An apparatus and method for controlling devices in a multiple bus system such as a system having two or more ISA type buses. Separate ISA bus controllers may be provided for each ISA bus, linked on a common bus system such as a PCI bus. One ISA controller may be designated as a primary ISA controller whereas other ISA controllers in the system may be designated as secondary ISA controllers. Each ISA controller in the system is provided with IRQ (interrupt request) enable bits to enable different interrupts for the corresponding ISA bus. Each secondary ISA controller outputs a signal IRQSER as a PCI sideband signal to the primary ISA controller to indicate which IRQs have been asserted on the respective ISA buses. The primary controller receives the IRQSER signal as well as the IRQ signals asserted on its own bus and converts these interrupt requests to PCI bus cycles.

Abstract: A pallet and pallet foot is made of corrugated materials such that the entire pallet and pallet foot may be recycled with other corrugated materials (e.g., boxes or the like). The pallet foot is made from shredded corrugated waste which is made into a slurry and molded, using a wet pulp process, to form a molded pallet foot. The pallet foot may be glued to a corrugated deck provided with cutouts in the deck surface. Cutouts accept pallet feet from another pallet such that multiple pallets may be stacked in a nesting manner. The pallet feet may be further fortified with a water resistant coating. The resulting pallet is lightweight, strong, and readily recyclable.

Abstract: A method and apparatus for improving performance of bit block transfers in display controllers during clipping functions without significantly increasing gate count. In a clipping function, particularly when transferring a portion of a monochrome bit map and color expanding same or in pattern copying, a source start address may not lie on a byte boundary. In order to avoid using time consuming shift left operations in software, the source start address may be adjusted in hardware to an earlier byte boundary. Upon writing data to a destination address, a hardware byte mask may be employed to prevent writing of the additional data retrieved due to the adjustment of the source start address. The source start address and byte mask hardware may be implemented in hardware using bit block transfer engine components and a small amount of additional hardware. The remainder of the clipping functions may remain in software, for example in a display device driver.

Abstract: A device for automatic testing of electrical high voltage lines is described, comprising a support (1), a driving wheel (2) for lying against the line (3) with a remotely controlled device (4) and a means for remotely controlled automatic measurement of physical data at the joint (11) in question). Means for the transfer of measurement data to a receiver is provided along with a shielding means (15) to shield the transfer means. The device is characterized primarily in that it is provided with a guide rails means (7,8,9) for steering of the device, carried by a lifting means such as a helicopter or crane for lying the driving wheel against a line. Physical measurement may comprise contacting as well as non-contacting measurement in the vicinity of and at a joint in question. To compensate for voltages which may be induced in the measuring means, a compensation circuit is provided. The compensation circuit may be provided with a flat coil which may be rotated by a stepper motor or the like.

Abstract: A coupling device for a tractor provided with a three point hitch. The coupling device has a first coupling frame, and a second coupling frame, provided with at least an upper and two lower fastening links for hinged fastening of a tool, the first coupling frame being provided with a first coupling element in longitudinally and directionally variable rotation connection with the rotating shaft of the tractor. The second coupling frame is provided with a second coupling element being rotatably connectable with the first coupling element, to transfer the effect of the rotating shaft to the tool. The coupling frames are provided with cooperating upper and lower fastening elements. The upper fastening element of the first coupling frame consists of two fastening hooks turned from the tractor, provided at a spaced horizontal distance from each other symmetrically from the vertical symmetric axis of the coupling frame, converging upwards towards each other.

Abstract: A method and apparatus for generating 3-D images utilizes an MPEG decoder to decode/decompress animated texture maps into a half-frame buffer. The MPEG decoder may act as a PCI bus master to assert control of the host system bus to the exclusion of all other system devices to transfer animated texture maps into an off-screen portion of video memory. A graphics subsystem generates a 3-D image from 3-D image data stored in display memory portion of video memory and superimposes the 3-D image with texture map data from the off-screen portion of video memory. Texture map data may be continually updated by MPEG decoder 360 on a periodic basis without interfering with the operation of the graphics subsystem. The resultant 3-D image with animated texture maps may provide a more realistic display, particularly for animated objects, such as a human face.

Abstract: A para-plane (parachute or parafoil airplane), ultralight, or the like is provided with a ducted propeller or fan to increase efficiency of the powerplant, thus reducing the size of the powerplant required. In addition, the duct may reduce propeller and/or engine noise and enhance safety for pilot, passengers and bystanders. Axial vanes may be provided upstream or downstream of the propeller within the duct to counteract the torque effect of the propeller. In another embodiment, a novel inflatable parafoil may be provided to reduce the effort required to initially inflate a prior art parafoil and reduce the incidence of ground strikes of the parafoil. The inflatable parafoil may be inflated with a buoyant gas such as helium or hot air to further reduce ground contacts and provide limited buoyancy to the aircraft.

Abstract: A memory controller, particularly for use in a video controller, is provided which reduces the effect of page misses during memory access. A video port FIFO is provided for buffering data from a video port to a display memory. A CRT FIFO is provided for buffering data from a display memory to a display. If, during a video port FIFO cycle, a page miss is encountered, the video port FIFO cycle is terminated and processing passes to a CRT FIFO CYCLE. If a page miss is encountered during a CRT FIFO cycle, the subsequent video port FIFO cycle will shortened by a number of memory cycles to compensate for the additional memory cycles required by the page miss. Additional data accumulated in the video port FIFO may be transferred to the display memory during a retrace interval. In this manner, memory bandwidth is optimized by removing a non-aligned page miss as the worst case of memory bandwidth utilization.

Abstract: A toothbrush holder comprises a generally planar support plate having at least one L-shaped slot formed at the periphery thereof, the L-shaped slot has a necked portion for retaining the toothbrush. The L-shaped slot may have a major axis and a minor axis. The minor axis of the L-shaped slot may intersect the periphery of the support plate. The necked portion may be provided at a position on the major axis of the L-shaped slot, positioned approximately halfway along the major axis of the L-shaped slot. In a second embodiment of the present invention, the L-shaped slot may be provided with a countersunk or counterbored portion provided along the major axis of the L-shaped slot to retain a toothbrush. The countersunk or counterbored portion may be provided at an end of the L-shaped slot furthest from the minor axis. In a third embodiment of the present invention, a milled portion may be provided along the major axis of the L-shaped slot to retain a toothbrush.

Abstract: Apparatus for use with standard television (TV) for superimposing images, captions, titles, or other information over the television scene. Synchronization of the superimposed images with the television scene is brought about by phase locking the images to the horizontal synchronization pulse train of the television scene. A joystick input device allows the television viewer to select from a library of superimposed images and to move the images to any location over the television scene. The viewer may continue to move the superimposed images over the television scene to set up and maintain humorous or other expressive effects. The apparatus can also be used as an educational tool in conjunction with appropriate broadcasted or recorded programming. Closed-graphics information received with a television signal may generate and control locally generated graphic overlay images to provide interactive gaming or educations applications.

Abstract: An automatic bus identification circuit is provided in a device to reliably detect system bus type on power up despite fluctuations in supply voltage. A system bus type signal is received over a multi-function input line at a first input and a reset signal received over a set line at a second input. A bus type identification circuitry is provided to latch the system bus type signal upon power up and continuously output this signal as a system bus type identification signal. To prevent the influence of disturbances in the power supply upon power-up, a flip-flip is provided to output a logic signal in response to a system reset signal. The flip-flop is configured with a strong-N type inverter to insure that the flip-flop will be set into a grounded state as power is applied to the circuit, despite the influence of transient power supply voltages.

Abstract: A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substantially synchronizing the display of video images with audio playback. An audio presentation time stamp (APTS) is detected in the compressed/coded audio data stream in the integrated system and video decoder and stored in a data latch. The compressed/coded audio data stream is fed to an audio decoder which decodes/decompresses the audio data and outputs and audio signal. The audio decoder detects when audio data corresponding to an APTS had been output and sets a corresponding flag. The flag indicates to the integrated system and video decoder that a corresponding audio segment had been decoded/decompressed and output.

Abstract: Precise and accurate determination of gypsum in soils has been difficult, laborious and time consuming by currently available methods. The present invention solves such problems by: 1) Direct removal of nongypsic sulfate from 2-g soil sample with 25-mL portion of 50-% (v/v) ethanol, thus, eliminating positive errors in gypsum measurement from sulfate analysis while causing essentially no loss in gypsum content of the sample, and 2) stoichiometric conversion of soil gypsum to Na.sub.2 SO.sub.4 and CaCO.sub.3 (s) by two equlibrations of the soil sediment with 25-mL increments of 0.5M Na.sub.2 CO.sub.3 solution plus 30-s sonification. The SO.sub.4 in the supernatent solution is centrifuge separated, analyzed by the standard BaSO.sub.4 gravimetric and turbidimetric methods, and gypsum content is computed from equation [8]:gypsum(g)/soil(kg)=[SO.sub.4 (g) /soil(kg)(172/96.

Abstract: A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substantially synchronizing the display of video images with audio playback. Latency between Audio and Video decompression/decoding may be adjusted dynamically by internal hardware. Hardware signals indicating the need to skip or repeat a frame or frames of video or audio data are fed to a hardware circuit which may increment or decrement a latency value accordingly. The latency value is thus stepwise incremented or decremented until no further frame skips/repeats occur. The hardware implementation allows for better matching of latency value to audio and video decoder, frees up software for other tasks and reduces software code requirements.

Abstract: The present invention is intended to provide a dispersion compensating optical fiber for wavelength division multiplex optical communication. A refractive index distribution of the dispersion compensating optical fiber is set to be W-shaped, an outside of a core is formed as an internal clad layer and the outside of the internal clad layer is formed as an outermost clad layer made of pure silica. Germanium for raising the refractive index by 2.8% in a specific refractive index difference is doped in the core, and fluorine is uniformly doped in the internal clad layer so that the refractive index is reduced by 0.45% in the specific refractive index difference. A diameter ratio of the core and the internal clad layer is set to be in a range of 1:1.5 to 1:4.0, a wavelength dispersion slope is set to be in a negative area, and dispersion is controlled to a negative high dispersion structure of -100 ps/km-nm or under.

Abstract: A DRAM interface, particularly for use in a video controller IC is provided with an improved technique for latching data from an extended data output (EDO) DRAM. An inactive column select CASn signal is fed back through the output of the DRAM interface, along with a write enable signal WEn, to emulate delays of such signals within the extended data output DRAM and the DRAm controller. The inactive CASn signal and write enable signal WEn are ANDed together to produce an ENABLE signal for latching data in a transparent latch. The use of the ENABLE signal optimizes the performance of the EDO DRAM and prevents collision of read and write data.

Abstract: A NAPNOP circuit for decreasing energy consumption of all or a portion of a microprocessor based system which includes a delay circuit for inhibiting or slowing the output of the system clock pulses for a variable length of time equal to a multiple of N clock pulses where N is a positive integer. The NAPNOP circuit has an input element for inputting a STARTNAP signal which begins a nap period during which the system clock pulses are inhibited or slowed, a clock input device for providing a plurality of selectable clock pulses as inputs to the delay circuit for controlling the operation of the computer system, and a gate element for terminating the nap period.