Abstract: A power supply module package suitable for both high packaged power density and cost effective manufacture. In an exemplary embodiment, the power supply module includes: (1) at least one printed circuit board containing conductors for interconnecting components of the power supply, (2) a thermally conductive baseplate or case operable for transferring heat generated inside the module to the outside environment, wherein the external package dimensions are of a sufficiently small size to allow the user the greatest flexibility in the design of the overall circuit assembly, (3) at least one power magnetic device operable for providing electrical isolation between the input and the output of the power module, and (4) a set of electrical leads to facilitate communication and power flow between the module and circuitry being powered.

Abstract: A synchronous rectifier for use with a clamped-mode power converter uses in one embodiment a hybrid rectifier with a MOSFET rectifying device active in one first cyclic interval of the conduction/nonconduction sequence of the power switch and a second rectifying device embodied in one illustrative embodiment as a low voltage diode rectifying device active during an alternative interval to the first conduction/nonconduction interval. The gate drive to the MOSFET device is continuous at a constant level for substantially all of the second interval which enhances efficiency of the rectifier. The diode rectifier device may also be embodied as a MOSFET device. The subject rectifier may be used in both forward and flyback power converters.

Abstract: System and method for enhancing the spatial effect of sound produced by a sound system. In an exemplary embodiment, the system includes a reverberator and a sound spatialization unit, which are a combination of filter(s), attenuator(s), differentiator(s), adder(s) and phase shifter(s). The present invention creates sound images at different spatial locations for different frequencies by employing a phase shifted high frequency reverberated signal. As a result, the loud speakers produce sound images located at several spatial positions, producing a perception that there is an array of loudspeakers surrounding a listener.

Abstract: System and method for creating a Doppler Effect signal in a virtual reality environment. A host produces: (1) an audio signal indicative of sound produced by a sound source, (2) a first set of signals indicative of a velocity of the sound source and an observer of the sound source, and (3) a second set of signals indicative of a position of the sound source and the observer. An interpolator interpolates the audio signal and generates an interpolation signal. A Doppler engine receives the first and second sets of signals and generates a decimation factor signal. A decimator filter, receives the interpolation signal and the decimation factor signal and generates a decimation signal. The decimation signal is a digital representation of said Doppler Effect signal and can be converted to an analog signal for broadcast to a listener.

Abstract: A rectifier architecture with a split boost circuit having protection circuitry for protecting circuit elements of the split boost. The split boost includes a voltage input terminal, an inductor, two voltage output terminals, a boost diode and branches A and B. Each branch A and B, includes: a switch, a protection circuit, and a capacitor. In a preferred embodiment, the protection circuit is a parallel resistor-diode pair coupled between the capacitor and the switch. The purpose of the protection circuit is to limit circulating current between capacitors when switches in branches A and B are active.

Abstract: A system and circuitry is provided by which certain selected embedded pins of an integrated circuit gate array may be provided with dual functions, that is to say, they may act either as receivers of an externally sourced input signal or as transmitters of an internally generated output signal. Each selected input/output pin is controlled by an associated flip-flop residing in a chain of flip-flops so that an associated flip-flop will determine the condition of two buffer-drivers attached to each input/output pin. While the first buffer-driver is tri-stated (disabled), then the embedded pin operates as an input receiving function. When the first buffer-driver is enabled, the embedded I/O pin operates as the conveyer of an output signal from the internal output logic.

Abstract: In a computer system having a user interface, a memory and a database, a repository program operating in the computer system for accessing the database, the repository program executing a method for treating a group of objects as a single object. This method comprises the steps of retrieving a collection of references for a type from the repository; sorting out each reference in the collection of references that are composite references and have a versioned object type; for each sorted reference, retrieving objects from the reference; and calling up current operations for each retrieved object.

Abstract: The present invention relates to a method and apparatus for automatically generating a knowledge base for use in an expert system. More specifically, the present invention discloses a method and system for automatically generating a knowledge base using a graphical programming environment to create a logical tree from which such a knowledge base may be generated. This enables a user of the present invention to author a knowledge base without knowledge of artificial intelligence specific languages and constructs. This is accomplished by permitting the user to construct a graphical picture that represents the problem solving knowledge about a given subject known as a decision tree, or logical tree. The arrangement of the graphical objects in the logical tree, along with the logical attachments associated with these objects, is used by the system employing the present invention to generate a knowledge base.

Abstract: A bridge circuit includes a microprocessor having a first I/O port which couples to a SCSI bus and a second I/O port which is coupled through transceivers to an EISA bus. Also, the bridge circuit includes an EISA interface controller, having control lines coupled to the EISA bus and the transceivers, which enable the microprocessor to request and use the EISA bus in time-shared fashion. In order to achieve a high speed of operation, the bridge circuit further includes a memory module, coupled via a private bus to the second I/O port of the microprocessor, which sends instructions on the private bus directly to the microprocessor, without generating any signals on the EISA bus. In addition, in order to prevent deadlocks on the private bus, the bridge circuit includes a deadlock prevention circuit which is coupled to the microprocessor and the private bus and the EISA interface controller.

Abstract: The present invention provides a multi-level memory system with a multi-level memory structure and methods for allocating data among the levels of memory based on the likelihood of imminent future use. The multi-level memory structure includes a first level memory that stores the data most likely to be imminently accessed, a second level memory that stores data transferred from the first level memory when the first level memory is full, and a third level memory that stores data that is the least recently used when the second level memory is full. According to the invention, predetermined criteria and statistics are used to determine which data is likely to be imminently accessed. Once the first level memory has been full, data stored in that memory level may be rearranged based on when it is likely to be accessed. The first level memory also provides for faster access than the second level memory which in turn provides faster access then the third level memory.

Abstract: A mini-cache module is added to a computer system to increase throughput or may also be added to enhance the functionality of a general cache memory unit. The mini-cache module refills and stores frequently used data words concurrently during processor operations and provides them to the processor, eliminating the need to access a system bus to main memory. A data queue storage stores a data block of words from main memory and makes them available to requests from the main processor (if the requested address matches an address register block in the mini-cache). If an address "hit" occurs, then the mini-cache will prevent any system bus request to main memory and additionally will monitor the system bus for any "Write" operations which might feasibly change the validity of data in the data storage block of the mini-cache. In this case the data stored in the mini-cache is invalidated and cannot be used by the processor.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the preset invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of a table.

Abstract: A method and a switching system for connecting multiple requestors to multiple memory units simultaneously. This is accomplished by a switching system that employs multiplexing logic, control logic, multiple data input and output ports and a unique system interconnection topology. Independent data input ports comprised of multiplexing logic controlled by a control logic, simultaneously channel multiple fetch and store commands from the requestors to the memory units. Similarly, independent data output ports comprised of a second multiplexing logic controlled by a second control logic, simultaneously channels multiple return signals from the memory units to the requestors. The switching system of the present invention incorporates the unique system interconnection topology concept of feed-through boards and modular backplane boards.

Abstract: An apparatus for blocking air and dust from entering a floppy disk drive. A floppy disk has a compressible non-porous dam (a non-porous foam strip material) attached to the front-tip edge of the floppy disk. When the floppy disk is inserted into the drive the dam compresses to conform to the volume of the drive opening. Accordingly, air as well as dust is blocked from the disk drive and air flow is improved within the computer cabinetry.

Abstract: Control signals are provided for data transfer timing compatibility between two systems or two modules which are not synchronous with each other. Specialized circuitry is provided to ensure timing compatibility in that control signals, transmitted from one system to the other, are handled by interface circuitry which directly transmits the front-end transition and delays the back-end transition so it can be synchronized to the receiving systems clock.

Abstract: Modular expansion of a backplane is achieved by means of a modular backplane circuit board that plugs into the backplane side of a backplane parallel to that backplane. The backplane board provides a parallel backplane path between boards on the computer system. When unit boards are added to the foreplane side which require additional electrical paths for connection purposes, a modular backplane board may be added to the backplane side of the backplane to provide such path. In the preferred embodiment a gate array is added to the backplane board to provide management functions in handling the electrical connections on the backplane board.

Abstract: The disclosed invention is an apparatus in a computer peripheral device for determining the direction of signal flow and data flow on a SCSI bus, which apparatus comprises a time delay means responsive to status signals of the SCSI bus. The time delay means generates a signal that defines an arbitration selection period of time for determining control of the SCSI bus. The apparatus further includes a first circuit means responsive to the arbitration selection signal and status signals of the SCSI bus. The first circuit means generates a plurality of signals that determine whether the peripheral device is an initiator of signals to be transmitted on the bus or is a target for receipt of signals present on the bus. Moreover, the apparatus includes a second circuit means that is responsive to the plurality of signals generated by the first circuit means and status signals of the bus. The second circuit means generates a pair of signals indicative of the direction of data and signal flow on the SCSI bus.

Abstract: An electronic tester, for testing I.sub.ddq in an integrated circuit chip, comprises: 1) a first power supply, having a large current capacity, which sends current to the chip through a first diode; 2) a second power supply, having a current sensor and a small current capacity which is substantially less than the large current capacity, which sends current to the chip through a second diode which is in parallel with the first diode; and 3) a control module which sends test vectors to the chip during a series of spaced apart T.sub.A time intervals, and sends control signals to at least one of the power supplies which indicate when the T.sub.A time intervals occur. In response to the control signals, the one power supply generates a first output voltage during the T.sub.A time intervals which forward biases said first diode and reverse biases said second diode; and it also generates a second output voltage between the T.sub.

Abstract: An interbus interface module enables storage and transfer of commands, messages and data between parallel a dual system bus operating on a first protocol and a subrequestor bus operating on a second protocol. The interface module serves a first group of requestors, such as multiple processors and main memory, for handling data transfers to and from the subrequestor bus via said dual system buses while also handling data transfers to and from a second group of requestors connected to the subrequestor bus.

Abstract: A buffer memory holding blocks of data received from a main host computer has dedicated portions for data destined for different sets of sender-receiver units. Each sender-receiver unit has a channel bus path to the buffer memory and each channel bus is monitored by an on-the-fly integrity checking circuit.A control processor and associated bus arbitration logic provide signals to a multiplexer so as to allocate equal access periods to each channel bus for connection to the buffer memory. A data feeder control on each transfer channel senses the availability of data block words in each dedicated segment of the buffer memory so that partial transfers of word blocks may occur on minor cycles with subsequent completion of the blocks of data words on a major transfer cycle.