Abstract: A memory module is used in multiples on a bus in a data processing system. Each memory module comprises a plurality of storage cells, an input circuit for receiving a read command and a read address from the bus, and a compare circuit which generates a match signal when the read address is within a selectable address range for the storage cells. Also, the module further includes: a control circuit, coupled to the compare circuit, which responds to the match signal by almost always executing the read command in a small time interval on the bus and occasionally executing the read command in a long time interval. Further, the module includes a bus transmit circuit, coupled to the control circuit, for sending a control signal on the bus if the control circuit selects the long time interval.