Patents Represented by Attorney, Agent or Law Firm Robert R. Jackson
  • Patent number: 7004420
    Abstract: The present invention is concerned with the driving mechanism of winding needles which dispense wire to form the wire coils of a dynamo-electric machine component. Generally, such wire winding is achieved by providing translational, rotational, and radial motions to the winding needle relative to a reference structure of the component. The present invention provides wire winding solutions for causing the winding needles to accomplish predetermined motions with respect to the component so that wire is predictably positioned on the component to form the wire coils. In particular, the present invention provides a driving mechanism with coaxial hollow shafts that impart the necessary motions to the winding needle. In one aspect of the invention, the inner shaft is able to mirror the rotation of the outer shaft to provide rotational motion to the winding needle.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: February 28, 2006
    Assignee: ATOP S.p.A.
    Inventors: Gianfranco Stratico, Antonio Lumini
  • Patent number: 6836164
    Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: December 28, 2004
    Assignee: Altera Corporation
    Inventors: Bonnie I. Wang, Joseph Huang, Chiakang Sung, Xiaobao Wang, In Whan Kim, Wayne Yeung, Khai Nguyen
  • Patent number: 6819135
    Abstract: A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: November 16, 2004
    Assignee: Altera Corporation
    Inventors: Christopher F. Lane, Srinivas T. Reddy
  • Patent number: 6815981
    Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: November 9, 2004
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
  • Patent number: 6792673
    Abstract: Hollow cylindrical dynamo-electric machine stator cores may be made by superimposing at least two strips of core material to produce a composite strip. One or more of the strips may be run through a pressure roller structure prior to super-positioning of the strips. The composite strip is coiled helically to produce the hollow cylindrical stator core. By pressure rolling at least one strip, the internal diameter of the stator core can be adjusted to reduce irregularities. By superimposing strips prior to coiling, thinner strips can be used without requiring the stator forming machine to operate longer or faster to produce stator cores of a given size. The pressure rolling aspects of the invention are also applicable to coiling apparatus that uses only a single strip. Stator cores may also be made by coaxially assembling and joining two coils with a hollow annular lamination disposed between the two axially spaced coils.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: September 21, 2004
    Assignee: Axis USA Inc.
    Inventors: Giorgio Barrera, Gianfranco Stratico, Andrea Bonnacorsi, Sandro Lombardi
  • Patent number: 6785109
    Abstract: A technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses is provided. The technique involves using a clamping device that is capable of handling both positive and negative ESD pulses to clamp each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. Without resorting to exhaustive cross-clamping, this arrangement provides a discharge path for an ESD pulse applied across any combination of power buses, ground buses, and I/O pads during an ESD event.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: August 31, 2004
    Assignee: Altera Corporation
    Inventors: Cheng H. Huang, Chiakang Sung, John Costello
  • Patent number: 6781408
    Abstract: A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD may also contain at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. In some cases, the FSB input routing channel may also include circuitry for performing elementary processing operations.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: August 24, 2004
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 6779758
    Abstract: A boom deploy actuator with improved maintainability and simplicity has an electric motor and control circuitry for selectively powering the motor to develop torque with either rotational direction for rotating a capstan to vary the length of a boom cord extending from the capstan to a boom. In a preferred embodiment, the motor is a brushless electric motor. The control circuitry preferably includes circuit components for limiting the speed of the motor.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: August 24, 2004
    Assignee: Smiths Aerospace, Inc.
    Inventors: Khoi T. Vu, Valentin G. Barba
  • Patent number: 6771105
    Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: August 3, 2004
    Assignee: Altera Corporation
    Inventors: Stjepan William Andrasic, Rakesh H. Patel, Chong H. Lee
  • Patent number: 6771585
    Abstract: An improved light-readable information recording medium is provided that comprises an optical data storage structure having lands and pits, in which the depth of the pits is about: λ 2 ⁢ n ⁢   ⁢   ⁢ M 1 + m T 2 , wherein &lgr; is the wavelength of light used to read the information recording medium, m is the order of interference selected from a group consisting of odd integers, MT is the transverse magnification, and n is the refractive index encountered by the reading light inside the pits.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: August 3, 2004
    Assignee: Wea Manufacturing, Inc.
    Inventors: Yajun Li, Emil Wolf
  • Patent number: 6771094
    Abstract: A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: August 3, 2004
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Gregory Starr, Chiao Kai Hwang
  • Patent number: 6762381
    Abstract: According to a method of producing a key top for a pushbutton switch of the present invention, a base layer made of an insulating resin that can be plated with metal, an electroless plating layer to be formed on the surface of the base layer, and a polymer coating layer, if required, are stacked on the surface of a key top body. Alternatively, an electroplating layer formed by electroplating is further formed on the electroless plating layer. Therefore, a plating layer can be directly and easily formed on the insulating resin, whereby a key top for a pushbutton switch having a sensation of metal and being rich in design is obtained.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: July 13, 2004
    Assignee: Polymatech Co., Ltd.
    Inventors: Tedi Kunthady, Atsushi Hikita
  • Patent number: 6759870
    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: July 6, 2004
    Assignee: Altera Corporation
    Inventors: Richard G. Cliff, Bahram Ahanin, Craig Schilling Lytle, Francis B. Heile, Bruce B. Pedersen, Kerry Veenstra
  • Patent number: 6754766
    Abstract: Circuitry that includes blocks of memory can be used to emulate a content addressable memory (“CAM”). The CAM data is stored in enough blocks of memory so that all of that data can be gradually read out in the time allowed for completion of a CAM search. As the data is read out, it is compared to CAM search data. If and when a match is found, a CAM address associated with the CAM data found to match the search data is generated. Alternatively or in addition, a simple “match” signal may be generated. If desired, the contents of the emulated CAM may be changed. To do this, circuitry is provided for converting the CAM address of the new data to an appropriate physical address (in the above-mentioned memory blocks) for that data.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: June 22, 2004
    Assignee: Altera Corporation
    Inventor: Guy R. Schlacter
  • Patent number: 6750675
    Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: June 15, 2004
    Assignee: Altera Corporation
    Inventors: Ramanand Venkata, Chong H. Lee, Rakesh Patel
  • Patent number: 6747480
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e.g., inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: June 8, 2004
    Assignee: Altera Corporation
    Inventors: Sinan Kaptanoglu, Michael D. Hutton, James Schleicher
  • Patent number: 6742172
    Abstract: A mask-programmable logic device that includes programmable gate array sites is provided. The gate array sites contain circuit elements that may be programmed to perform certain logic functions that correct problems associated with implementing a preexisting circuit design in mask-programmable device.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: May 25, 2004
    Assignee: Altera Corporation
    Inventor: Jonathan Park
  • Patent number: 6737885
    Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 18, 2004
    Assignee: Altera Corporation
    Inventors: Sergey Y. Shumarayev, Thomas H. White
  • Patent number: 6738962
    Abstract: An integrated circuit includes programmable logic circuitry and control circuitry that is operable to enable the integrated circuit to make a connection to an external source of data for configuring the programmable logic circuitry. The integrated circuit may include dedicated communications port circuitry that can be used in making the above-mentioned connection, or the programmable logic circuitry itself can be configured for operation as communications port circuitry for use in making the connection. The programmable logic circuitry may be configured any number of times.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: May 18, 2004
    Assignee: Altera Corporation
    Inventors: Edward Flaherty, Mark Dickinson
  • Patent number: 6732971
    Abstract: In systems for winding wire on electrodynamic machine stators, stators may be transferred between stator conveyance apparatus, winding shroud installation and removal apparatus, wire winding apparatus, wire lead termination apparatus, or other apparatus. Some transfer devices may secure stators in housings fixed to arms that may be rotated around an axis to move stators between stations. Some transfer devices may have stator grasping devices that may be rotated and translated to move stators between stations. Wire winding shrouds may be secured to a stator to facilitate winding and released from stator after wire is wound on the stator. A device for securing shrouds to the stator may be fixed to the stator and may remain fixed to the stator during transfer between different apparatus. Some devices for securing shrouds and stators may be integrated into housings. Some housings may be fixed to transfer devices along one side of the housing.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: May 11, 2004
    Assignee: Axis U.S.A., Inc.
    Inventors: Gianfranco Stratico, Maurizio Mugelli, Antonio Lumini