Abstract: An integrated electronic control circuit comprises a microcontroller connected to at least one volatile memory, at least one input/output port, a plurality of control devices, and an electronic non-volatile memory device comprising a non-volatile memory cell matrix linked to a control register, and a switch element connected between a voltage reference and the cell matrix to enable the program mode of the cell matrix under control by the microcontroller.

Abstract: The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of:defining an isolation region on a layer of silicon oxide overlying a silicon layer;selectively etching the silicon to provide the isolation region;growing thermal oxide over the interior surfaces of the isolation structure;depositing dielectric conformingly; andoxidizing the deposited dielectric.

Abstract: A sectorized electrically erasable and programmable non-volatile memory device comprises: a plurality of individually-addressable memory sectors, each memory sector comprising an array of memory cells arranged in rows and columns; redundancy columns of redundancy memory cells for replacing defective columns of memory cells; and a redundancy control circuit for storing addresses of the defective columns and activating respective redundancy columns when said defective columns are addressed. Each memory sector comprises at least one respective redundancy column.

Abstract: A power supply circuit for driving a capacitive load includes a driving pulse generation circuit that generates a driving pulse of a specified frequency, a single drive circuit that is controlled by this driving pulse, and an autotransformer, where a center tap is connected to a source voltage, and forms a resonant circuit by using an autotransformer and a capacitive load, which is connected thereto. Alternatively, instead of driving pulse generation circuit, it includes a differential amplifier and a positive feedback path that performs positive feedback from one of the terminals of the autotransformer to the input terminal of the differential amplifier. In this manner, by driving the autotransformer using the single drive circuit, the entire autotransformer can be utilized in an efficient manner and a smaller and cheaper power supply circuit can be realized.

Abstract: A voltage level shift circuit has a first input receiving a first voltage signal and a second input receiving a second voltage signal. The voltage level shift circuit is structured to generate an output voltage at an output terminal which is equal to a sum of the first and second voltage signals. The first voltage signal may be varied to vary a shift of the second voltage signal.

Abstract: A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material, specifically silicon oxynitride or silicon nitride, on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material (silicon oxynitride or silicon nitride particularly) overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2), silicon dioxide in the preferred embodiment, is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

Abstract: An integrated semiconductor circuit comprising an output terminal connected to a ground terminal via a series connection of a first switching transistor and a second switching transistor of inverse polarization with respect to the latter, each of said switching transistors having parasitic transistors. Whether the second semiconductor switch means is conducting or not, is dependent on the current flow through a resistor connected between gate and source of the second semiconductor switch means. Whether current flows through this resistor, is dependent on the switching condition of a further switching transistor, which in turn is also determined by the output signal of a comparator circuit by means of which a potential corresponding to the potential present at output terminal is compared to a reference potential.

Abstract: A power terminal is connected to a DC power source. A differential amplifier has primary and secondary input terminals and an output terminal, and a device applies a reference voltage to the secondary input terminal of the differential amplifier. A phase inverter has an input terminal connected to the output terminal of the differential amplifier and has primary and secondary output terminals that output two output signals of opposite phase. A push-pull drive circuit has primary and secondary input terminals connected to the primary and secondary output terminals of the phase inverter, and has primary and secondary output terminals connected to a switching element that alternately turns on and off by being driven by the two output signals of opposite phase that are provided from the output terminals of the phase inverter.