Abstract: One or more Central Processing Complexes (CPC), each with one or more programs being executed, become command initiators by issuing commands requesting an action to be performed by a command responder. The responder is a Structured Electronic Storage (SES) which comprises a coupling facility. The SES receives commands to be executed over a plurality of links interconnecting the CPC's and SES, and returns a response to the program that issued the command. The SES is the focal point for the CPC's to share data, control locks, and manipulate lists or queues. This couples the autonomous CPC's into a System Complex (Sysplex) displaying a single system image. An indicator associated with each of the links is set by SES when it appears to a initiator that problems on the link exist. The set state of any indicator prevents SES from starting execution of any subsequent commands.

Abstract: A functional unit designed with arithmetic pipelining for vector processing is attached to a base data processor from which it receives vector instructions and operands for processing. Stepping of operands and exception indicators through the vector processing unit is controlled by the base processor. Exception information transferred to the base processor is controlled to provide precise indicators of error conditions for recovery and restart of vector processing. Masking logic provides for expansion/contraction of operands in the vector processing unit as compared with sequential main memory addresses.

Abstract: A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.

Abstract: A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n.Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.

Abstract: According to the present invention, each data (one byte data in the embodiments described below) is transferred three times in total. The original data is transferred as it is on one time, a data made by inverting the original data is transferred on another time, and a data made by permuting all bits of the original data on the remaining time. A receiver reconstructs the data by reconverting the inverted and bit permuted data to their original forms and determining a majority among these data and the separately transferred original data. The bit permuted data is generated, for example, by rotating right or left the original data by a predetermined number of bits utilizing a recirculating shift register. The receiver must perform a bit permuting operation which is reverse to that of the sender.

Abstract: Method and apparatus for displaying maps on which the roads have width as well as length. The input to the system is a list of end points of line segments. The system operates upon this list to create a new set of line segment end points, defining two line segments for each one of the input line segments. The new line segments define roads having a predetermined width.

Abstract: An address word (N) for addressing a memory (2) comprises an exponent field (P) that defines on one hand the number of basic data units or accesses to be made to a memory, on the other a number by which a second field (M) in the address word is modified, the memory initially being addressed by the modified second field.

Abstract: A data processing system in which a process having a low priority may be interrupted by a process having a higher priority and in which an interrupted process ceases its current operation immediately the interrupt occurs, a mechanism by which the higher priority interrupting process finishes the interrupted operation of the lower priority process before commencing its own next operation.

Abstract: Each of a plurality of stored pointers identifies and accesses one of a plurality of hardware registers in a central processing unit (CPU). Each pointer is associated with and corresponds to one of a limited number of general purpose registers addressable by various fields in a program instruction of the data processing system. At least one program instruction calls for transfer of data from a particular main storage location to a general purpose register (GPR) identified by a field in the program instruction. The GPR identified as the destination for the data is renamed by assigning a pointer value to provide access to one of the plurality of associated hardware registers. A subsequent load instruction involving the same particular main storage location determines if the data from the previous load instruction is still stored in one of the hardware registers and determines the associated pointer value.

Abstract: A binary number substitution mechanism includes first and second storage arrays addressed by first and second portions, respectively, of an input binary number, producing a substitute output binary number. The input binary number represents a predetermined number of microinstruction addresses in a read-only store, and the output binary number is representative of microinstruction addresses in a main storage device. Only a limited number of the possible input binary numbers are required to access the first and second storage arrays to read out selectively stored binary numbers to create a limited range of output binary numbers unique to each of the limited number of the input binary numbers.

Abstract: The range of output binary numbers from a number substitution mechanism receiving input binary numbers, and which include first and second storage arrays addressed by first and second of the input binary number is substantially reduced by interleaving alternate output signals from the storage arrays which have been provided selectable binary numbers in certain storage locations accessed by certain ones of the input binary numbers. Further, compression of the range of output of binary numbers as substitution for certain ones of the binary input binary number is achieved by addressing the first and second storage arrays by first and second portions of the input binary number to which a certain number of the input signal line of the first and second portions are common.

Abstract: One program in one address space is permitted to obtain access to data in another address space or to call a program in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. A second address space can be designated by a program, and when authorized, can cause transfer of data in main memory from one physical location to another associated with the different address space. A program changeable space selection control bit controls use of two different sets of address translation tables associated with two different address spaces. Without invoking a supervisor, a particular program in an assigned address space can call a program in another address space or obtain addressability to data in another address space having an associated set of address translation tables.

Abstract: In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.

Abstract: A method of brazing two surfaces together with a Au/Sn brazing solder. The method includes the additional step of providing a film of Cu, for example on one of the surfaces, in addition to the Au/Sn brazing solder.

Abstract: The instruction register (IR), of a data processing system, stores a program instruction during at least an initial operation code decoding phase to initiate execution of the instruction. The IR (13) has a number of input gates in addition to the input gates from a program storing main storage device. The additional input gates respond to control or logic signals for gating information from the data flow hardware (40) to the instruction register.

Abstract: Buffered, pre-fetched instructions in the instruction handling portion of a data processing system are examined to detect sequences of predetermined instructions to effect generation of a substitute instruction to be executed by an execution unit in place of the first instruction of the sequence to perform the functions specified by all of the instructions of the sequence.

Abstract: Permits one program in one address space to obtain access to data in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. Addressability to a second address space may be specified by a program if authorized in accordance with the entry of an authority table associated with the second address space, the entry being designated by an authorization index associated with the program.

Abstract: A microinstruction control storage mechanism includes a read-only store (ROS), writeable control store (WCS), first cycle control store, and a reserved portion of main storage in a data processing system. The ROS stores frequently used sequences of microinstructions and is not altered during operation. Other sequences of microinstructions which are not frequently used are stored in the reserved portion of main storage. As required, blocks of microinstructions are paged into the WCS from the main storage. One cycle of execution is saved for each machine instruction by utilizing the operation code portion directly from the instruction register of the data processing system to access a microinstruction from the first cycle control store. An array of single-bit storage devices, accessed by microinstruction addresses also utilized to access microinstructions from the ROS, signal the existence of a faulty microinstruction from the ROS as determined by maintenance or design personnel.

Abstract: A communication system includes a plurality of requestors and a plurality of responders representing resources. A protocol exercised by all elements provides accurate and consistent interconnection of all elements in a system where messages may be delayed or lost. Requestors are provided with means to transmit a request for use of a plurality of resources, respond to acceptances from one or more responders and create a cooperative relationship by transmitting a confirmation to one responder and cancellation of the request to all other responders. Responders become committed to a requestor by signalling an acceptance to a request if a previous acceptance has not been transmitted, or if the resource is not already committed to another requestor, and a subsequent confirmation signal is received. The responder does not become committed after transmitting an acceptance if the next signal directed to it from the requestor is a request cancellation.

Abstract: Permits one program in one address space to obtain access to data in another address space or to call a program in another address space without invoking a supervisor, with authorization to use a storage protect key other than that specifically assigned to the program by a supervisor when in a new semi-privileged state. Programs executing in a particular address space have supervisor assigned storage protect key masks permitting the program, when authorized, to utilize a storage protect key other than the one specifically assigned by the supervisor. A second address space can be designated by a program, and when authorized, can cause transfer of data in main memory from one physical location to another associated with the different address space, and two different storage protect keys can be utilized.