Abstract: A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

Abstract: A porous polymeric bearing is formed of a sintered composite of polyphenylene sulfide and a cured condensation thermosetting resin such as a phenolic compound wherein the presence of the thermoset material affords structural support during the sintering of the polyphenylene sulfide and further induces highly interconnected porosity in the fabricated composite adaptable for impregnation with a liquid lubricant. The fabrication includes a curing and degassing of the compressed greenware bearing followed by sintering and a subsequent post cure.

Abstract: A single chip large scale integration processor possesses its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

Abstract: The disclosure is directed to a combined same cycle and subsequent cycle control of an injection molding machine. Mold cavity pressure readings are accumulated and averaged during an initial cycle portion to generate a sensed average value which is compared to a setpoint reference to test for an error. The error signal so generated is used to immediately vary the hydraulic pressure driving the injection ram during the same cycle of machine operation to cause the sensed pressure profile to be corrected to a reference pressure profile. A further correction to the hydraulic pressure is enabled as cavity pressure readings are continued to a later event, averaged, and the resulting sensed value compared to a setpoint reference to enable a further correction to be implemented during the same cycle although its effect on the process is principally effective in the next subsequent cycle.

Abstract: A cassette storage device retains cassettes in arcuately spaced relation for rotation about a horizontal axis which provides visual access with the cassettes being received in channels that confine end portions. Retention is affected by the use of the bosses on the cassette which are retained in slotted openings in web surfaces of the channels and releasability is achieved by the resiliency of the material which forms the holder.

Abstract: An FET read only memory array having bit locations arranged in rows and columns utilizes a dynamic array and static sensing. A dynamic first address selects the gate line of a selected column and a second address selects the source line or lines to select one or more bits within the selected column. The presence or absence of a gate at a selected bit location determines whether a first or second logic level is present at the sense or drain line serving the bit location. An additional column of FET bit positions each with a gate has the gate line activated toward the conclusion of the cycle to provide a path to ground for the elimination of any charge on a sense line in preparation for the next succeeding cycle. The sensed output from a selected bit location is latched until reset.

Abstract: A cable clamp and strain relief device is formed as a single piece from sheet material with a turned spring arm which provides a cable retaining, strain relieving function and a pair of depending leg members formed by flanging material at each transverse margin. The leg members each terminate in a turned distal end and are received in a pair of apertures in a cooperating plate. The terminal part of the distal end has a central tab with shoulders at each side such that normally the central tab springs out beneath the lower surface upon insertion through the apertures, but when insertion is restricted the shoulders may engage the plate lower surface adjoining the aperture to retain the clamp.

Abstract: In a control unit having a read only memory, a control program is provided which has provision for all features with which the machine may be equipped and for a selected number of future features. The control program contains one or more mainline control loops which interrogate mainline and feature functions sequentially to determine whether a function requires service. If a function is present and requires service, the appropriate routine is executed whereafter the mainline control program proceeds to execute the next indicated control program instruction. If a function is present, but does not require service, a normal return or other procedure is executed to return to the control loop. When a feature is addressed which is not present, a feature return is executed forcing the control program back to the instruction following the last branch.